Hi all,
I built Android 5.1.1 on imx6q-sabre SD, my custom board uses 2G DRAM, u-boot is Version 2015.04 , I had test my ddr with i.MX6/7 DDR Stress Test Tool V2.40 and got the calibration result, now I need to apply this change into u-boot, otherwise my custom board can't run correctly, i found u-boot source code is different from the version before, I have search the whole community for how to modify the new u-boot, but without lucky.
could somebody help chage DRAM from 1G to 2G on u-boot 2015.04?
Best regards
toot
解決済! 解決策の投稿を見る。
i followed this post:
change the DRAM parameter on my custom board, 4 piece k4b4g1646d DRAM (total 2G bytes) run very well,
here is the calibration result:
============================================
DDR Stress Test (2.4.0)
Build: Dec 11 2015, 11:13:38
Freescale Semiconductor, Inc.
============================================
============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================
============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x22000001
============================================
ARM Clock set to 1GHz
============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================
Current Tempareture: 49
============================================
DDR Freq: 528 MHz
ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00260022
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B002B
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001D0028
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000D0028
Write DQS delay result:
Write DQS0 delay: 34/256 CK
Write DQS1 delay: 38/256 CK
Write DQS2 delay: 43/256 CK
Write DQS3 delay: 43/256 CK
Write DQS4 delay: 40/256 CK
Write DQS5 delay: 29/256 CK
Write DQS6 delay: 40/256 CK
Write DQS7 delay: 13/256 CK
Starting DQS gating calibration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BYTE 0:
Start: HC=0x01 ABS=0x70
End: HC=0x04 ABS=0x34
Mean: HC=0x03 ABS=0x12
End-0.5*tCK: HC=0x03 ABS=0x34
Final: HC=0x03 ABS=0x34
BYTE 1:
Start: HC=0x01 ABS=0x4C
End: HC=0x04 ABS=0x28
Mean: HC=0x02 ABS=0x79
End-0.5*tCK: HC=0x03 ABS=0x28
Final: HC=0x03 ABS=0x28
BYTE 2:
Start: HC=0x01 ABS=0x54
End: HC=0x04 ABS=0x14
Mean: HC=0x02 ABS=0x73
End-0.5*tCK: HC=0x03 ABS=0x14
Final: HC=0x03 ABS=0x14
BYTE 3:
Start: HC=0x00 ABS=0x4C
End: HC=0x04 ABS=0x1C
Mean: HC=0x02 ABS=0x34
End-0.5*tCK: HC=0x03 ABS=0x1C
Final: HC=0x03 ABS=0x1C
BYTE 4:
Start: HC=0x01 ABS=0x60
End: HC=0x04 ABS=0x34
Mean: HC=0x03 ABS=0x0A
End-0.5*tCK: HC=0x03 ABS=0x34
Final: HC=0x03 ABS=0x34
BYTE 5:
Start: HC=0x01 ABS=0x60
End: HC=0x04 ABS=0x24
Mean: HC=0x03 ABS=0x02
End-0.5*tCK: HC=0x03 ABS=0x24
Final: HC=0x03 ABS=0x24
BYTE 6:
Start: HC=0x01 ABS=0x38
End: HC=0x03 ABS=0x5C
Mean: HC=0x02 ABS=0x4A
End-0.5*tCK: HC=0x02 ABS=0x5C
Final: HC=0x02 ABS=0x5C
BYTE 7:
Start: HC=0x01 ABS=0x58
End: HC=0x04 ABS=0x1C
Mean: HC=0x02 ABS=0x79
End-0.5*tCK: HC=0x03 ABS=0x1C
Final: HC=0x03 ABS=0x1C
DQS calibration MMDC0 MPDGCTRL0 = 0x03280334, MPDGCTRL1 = 0x031C0314
DQS calibration MMDC1 MPDGCTRL0 = 0x03240334, MPDGCTRL1 = 0x031C025C
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
ABS_OFFSET=0x10101010 result[04]=0x00011011
ABS_OFFSET=0x14141414 result[05]=0x00011011
ABS_OFFSET=0x18181818 result[06]=0x00011001
ABS_OFFSET=0x1C1C1C1C result[07]=0x00011000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x01100010
ABS_OFFSET=0x64646464 result[19]=0x01100111
ABS_OFFSET=0x68686868 result[1A]=0x01100111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11100111
ABS_OFFSET=0x70707070 result[1C]=0x11100111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
Byte 0: (0x1c - 0x60), middle value:0x3e
Byte 1: (0x18 - 0x5c), middle value:0x3a
Byte 2: (0x10 - 0x60), middle value:0x38
Byte 3: (0x20 - 0x70), middle value:0x48
Byte 4: (0x20 - 0x70), middle value:0x48
Byte 5: (0x10 - 0x5c), middle value:0x36
Byte 6: (0x10 - 0x5c), middle value:0x36
Byte 7: (0x10 - 0x68), middle value:0x3c
MMDC0 MPRDDLCTL = 0x48383A3E, MMDC1 MPRDDLCTL = 0x3C363648
Starting Write calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x10111111
ABS_OFFSET=0x08080808 result[02]=0x10111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x10110111
ABS_OFFSET=0x10101010 result[04]=0x10100011
ABS_OFFSET=0x14141414 result[05]=0x10100010
ABS_OFFSET=0x18181818 result[06]=0x00100000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00100000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x00000000
ABS_OFFSET=0x68686868 result[1A]=0x00001000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x01001000
ABS_OFFSET=0x70707070 result[1C]=0x01001110
ABS_OFFSET=0x74747474 result[1D]=0x01011111
ABS_OFFSET=0x78787878 result[1E]=0x01011111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
Byte 0: (0x14 - 0x70), middle value:0x42
Byte 1: (0x18 - 0x6c), middle value:0x42
Byte 2: (0x10 - 0x6c), middle value:0x3e
Byte 3: (0x0c - 0x64), middle value:0x38
Byte 4: (0x10 - 0x70), middle value:0x40
Byte 5: (0x20 - 0x78), middle value:0x4c
Byte 6: (0x04 - 0x68), middle value:0x36
Byte 7: (0x18 - 0x78), middle value:0x48
MMDC0 MPWRDLCTL = 0x383E4242,MMDC1 MPWRDLCTL = 0x48364C40
MMDC registers updated from calibration
Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00260022
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B002B
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001D0028
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000D0028
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x03280334
MPDGCTRL1 PHY0 (0x021b0840) = 0x031C0314
MPDGCTRL0 PHY1 (0x021b483c) = 0x03240334
MPDGCTRL1 PHY1 (0x021b4840) = 0x031C025C
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x48383A3E
MPRDDLCTL PHY1 (0x021b4848) = 0x3C363648
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x383E4242
MPWRDLCTL PHY1 (0x021b4850) = 0x48364C40
Success: DDR calibration completed!!!
Device Information | |
Manufacturer: | samsung |
Memory part number: | k4b4g1646d |
Memory type: | DDR3-1600 |
DRAM density (Gb) | 4 |
DRAM Bus Width | 16 |
Number of Banks | 8 |
Number of ROW Addresses | 15 |
Number of COLUMN Addresses | 10 |
Page Size (K) | 2 |
Self-Refresh Temperature (SRT) | Normal |
tRCD=tRP=CL (ns) | 13.75 |
tRC Min (ns) | 48.75 |
tRAS Min (ns) | 35 |
System Information | |
i.Mx Part | i.Mx6Q |
Bus Width | 64 |
Density per chip select (Gb) | 16 |
Number of Chip Selects used | 1 |
Total DRAM Density (Gb) | 16 |
DRAM Clock Freq (MHz) | 528 |
DRAM Clock Cycle Time (ns) | 1.894 |
Address Mirror (for CS1) | Disable |
SI Configuration | |
DRAM DSE Setting - DQ/DQM (ohm) | 48 |
DRAM DSE Setting - ADDR/CMD/CTL (ohm) | 48 |
DRAM DSE Setting - CK (ohm) | 48 |
DRAM DSE Setting - DQS (ohm) | 48 |
System ODT Setting (ohm) | 60 |
i followed this post:
change the DRAM parameter on my custom board, 4 piece k4b4g1646d DRAM (total 2G bytes) run very well,
here is the calibration result:
============================================
DDR Stress Test (2.4.0)
Build: Dec 11 2015, 11:13:38
Freescale Semiconductor, Inc.
============================================
============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================
============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x22000001
============================================
ARM Clock set to 1GHz
============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================
Current Tempareture: 49
============================================
DDR Freq: 528 MHz
ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00260022
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B002B
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001D0028
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000D0028
Write DQS delay result:
Write DQS0 delay: 34/256 CK
Write DQS1 delay: 38/256 CK
Write DQS2 delay: 43/256 CK
Write DQS3 delay: 43/256 CK
Write DQS4 delay: 40/256 CK
Write DQS5 delay: 29/256 CK
Write DQS6 delay: 40/256 CK
Write DQS7 delay: 13/256 CK
Starting DQS gating calibration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BYTE 0:
Start: HC=0x01 ABS=0x70
End: HC=0x04 ABS=0x34
Mean: HC=0x03 ABS=0x12
End-0.5*tCK: HC=0x03 ABS=0x34
Final: HC=0x03 ABS=0x34
BYTE 1:
Start: HC=0x01 ABS=0x4C
End: HC=0x04 ABS=0x28
Mean: HC=0x02 ABS=0x79
End-0.5*tCK: HC=0x03 ABS=0x28
Final: HC=0x03 ABS=0x28
BYTE 2:
Start: HC=0x01 ABS=0x54
End: HC=0x04 ABS=0x14
Mean: HC=0x02 ABS=0x73
End-0.5*tCK: HC=0x03 ABS=0x14
Final: HC=0x03 ABS=0x14
BYTE 3:
Start: HC=0x00 ABS=0x4C
End: HC=0x04 ABS=0x1C
Mean: HC=0x02 ABS=0x34
End-0.5*tCK: HC=0x03 ABS=0x1C
Final: HC=0x03 ABS=0x1C
BYTE 4:
Start: HC=0x01 ABS=0x60
End: HC=0x04 ABS=0x34
Mean: HC=0x03 ABS=0x0A
End-0.5*tCK: HC=0x03 ABS=0x34
Final: HC=0x03 ABS=0x34
BYTE 5:
Start: HC=0x01 ABS=0x60
End: HC=0x04 ABS=0x24
Mean: HC=0x03 ABS=0x02
End-0.5*tCK: HC=0x03 ABS=0x24
Final: HC=0x03 ABS=0x24
BYTE 6:
Start: HC=0x01 ABS=0x38
End: HC=0x03 ABS=0x5C
Mean: HC=0x02 ABS=0x4A
End-0.5*tCK: HC=0x02 ABS=0x5C
Final: HC=0x02 ABS=0x5C
BYTE 7:
Start: HC=0x01 ABS=0x58
End: HC=0x04 ABS=0x1C
Mean: HC=0x02 ABS=0x79
End-0.5*tCK: HC=0x03 ABS=0x1C
Final: HC=0x03 ABS=0x1C
DQS calibration MMDC0 MPDGCTRL0 = 0x03280334, MPDGCTRL1 = 0x031C0314
DQS calibration MMDC1 MPDGCTRL0 = 0x03240334, MPDGCTRL1 = 0x031C025C
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
ABS_OFFSET=0x10101010 result[04]=0x00011011
ABS_OFFSET=0x14141414 result[05]=0x00011011
ABS_OFFSET=0x18181818 result[06]=0x00011001
ABS_OFFSET=0x1C1C1C1C result[07]=0x00011000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x01100010
ABS_OFFSET=0x64646464 result[19]=0x01100111
ABS_OFFSET=0x68686868 result[1A]=0x01100111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11100111
ABS_OFFSET=0x70707070 result[1C]=0x11100111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
Byte 0: (0x1c - 0x60), middle value:0x3e
Byte 1: (0x18 - 0x5c), middle value:0x3a
Byte 2: (0x10 - 0x60), middle value:0x38
Byte 3: (0x20 - 0x70), middle value:0x48
Byte 4: (0x20 - 0x70), middle value:0x48
Byte 5: (0x10 - 0x5c), middle value:0x36
Byte 6: (0x10 - 0x5c), middle value:0x36
Byte 7: (0x10 - 0x68), middle value:0x3c
MMDC0 MPRDDLCTL = 0x48383A3E, MMDC1 MPRDDLCTL = 0x3C363648
Starting Write calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x10111111
ABS_OFFSET=0x08080808 result[02]=0x10111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x10110111
ABS_OFFSET=0x10101010 result[04]=0x10100011
ABS_OFFSET=0x14141414 result[05]=0x10100010
ABS_OFFSET=0x18181818 result[06]=0x00100000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00100000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x00000000
ABS_OFFSET=0x68686868 result[1A]=0x00001000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x01001000
ABS_OFFSET=0x70707070 result[1C]=0x01001110
ABS_OFFSET=0x74747474 result[1D]=0x01011111
ABS_OFFSET=0x78787878 result[1E]=0x01011111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
Byte 0: (0x14 - 0x70), middle value:0x42
Byte 1: (0x18 - 0x6c), middle value:0x42
Byte 2: (0x10 - 0x6c), middle value:0x3e
Byte 3: (0x0c - 0x64), middle value:0x38
Byte 4: (0x10 - 0x70), middle value:0x40
Byte 5: (0x20 - 0x78), middle value:0x4c
Byte 6: (0x04 - 0x68), middle value:0x36
Byte 7: (0x18 - 0x78), middle value:0x48
MMDC0 MPWRDLCTL = 0x383E4242,MMDC1 MPWRDLCTL = 0x48364C40
MMDC registers updated from calibration
Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00260022
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B002B
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001D0028
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x000D0028
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x03280334
MPDGCTRL1 PHY0 (0x021b0840) = 0x031C0314
MPDGCTRL0 PHY1 (0x021b483c) = 0x03240334
MPDGCTRL1 PHY1 (0x021b4840) = 0x031C025C
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x48383A3E
MPRDDLCTL PHY1 (0x021b4848) = 0x3C363648
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x383E4242
MPWRDLCTL PHY1 (0x021b4850) = 0x48364C40
Success: DDR calibration completed!!!
Device Information | |
Manufacturer: | samsung |
Memory part number: | k4b4g1646d |
Memory type: | DDR3-1600 |
DRAM density (Gb) | 4 |
DRAM Bus Width | 16 |
Number of Banks | 8 |
Number of ROW Addresses | 15 |
Number of COLUMN Addresses | 10 |
Page Size (K) | 2 |
Self-Refresh Temperature (SRT) | Normal |
tRCD=tRP=CL (ns) | 13.75 |
tRC Min (ns) | 48.75 |
tRAS Min (ns) | 35 |
System Information | |
i.Mx Part | i.Mx6Q |
Bus Width | 64 |
Density per chip select (Gb) | 16 |
Number of Chip Selects used | 1 |
Total DRAM Density (Gb) | 16 |
DRAM Clock Freq (MHz) | 528 |
DRAM Clock Cycle Time (ns) | 1.894 |
Address Mirror (for CS1) | Disable |
SI Configuration | |
DRAM DSE Setting - DQ/DQM (ohm) | 48 |
DRAM DSE Setting - ADDR/CMD/CTL (ohm) | 48 |
DRAM DSE Setting - CK (ohm) | 48 |
DRAM DSE Setting - DQS (ohm) | 48 |
System ODT Setting (ohm) | 60 |
I also met you in this case, how do you deal with
Please refer to the Chapter 1 of the attached document. This document can also be found as the part of the L3.14.52_1.1.0_LINUX_DOCS bundle, available on the public NXP web site (check the "Supporting Information" section):
Have a great day,
Artur
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Hi artur ,
Thanks for replying, according to L3.14.52_1.1.0_LINUX_DOCS Chapter 1, I modify the register's value as following:
MMDC registers updated from calibration
Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0022001D
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00260028
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F0028
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x00150028
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x431C0330
MPDGCTRL1 PHY0 (0x021b0840) = 0x03140314
MPDGCTRL0 PHY1 (0x021b483c) = 0x43240334
MPDGCTRL1 PHY1 (0x021b4840) = 0x03180258
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x4232383A
MPRDDLCTL PHY1 (0x021b4848) = 0x38363444
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x3A3A3E3C
MPWRDLCTL PHY1 (0x021b4850) = 0x46344842
then I recompile u-boot and boot my board with this cmd:
> sb_loader.exe -f u-boot-imx6q.imx
the u-boot start-up message still showing my board is DRAM: 1 GiB
could you tell me where to change the DRAM parameter ?
I attached my DDR calibration result below.
best regards
toot
Refer to the Section 1.2.1 "Preparing the Code" of the document I've sent to you. Pay attention to the configuration parameters, such as PHYS_SDRAM_SIZE and CONFIG_NR_DRAM_BANKS.
Best Regards,
Artur
Hi artur ,
i have configs as following;
#defined CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_SIZE SZ_2G
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR ( MMDC0_ARB_BASE_ADDR = 0x10000000 defined in arch/arm/include/asm/arch-mx6/imx-regs.h )
but u-boot still show me 1G DRAM , could you tell me how to config this marcos ?
best regards
toot