Hi all,
I am using flexspi interface on a IMX8MM to talk to an FPGA that simulates flash in SDR mode on 4 data lines (maybe DDR later). I'm using AHB bus cmd mode, and toggle between custom write and read QUAD cmds :
- custom write LUT cmd, without address section (to gain bandwidth)
- instruction 0 is the LUT cmd, SPINOR_OP_PP (QUAD)
- instruction 1 is the QUAD WRITE. I thought the operand was the data size, but it has no impact on the amount of data sent.
- custom read LUT cmd, without address section (to gain bandwidth)
- instruction 0 is the LUT cmd SPINOR_OP_READ (QUAD)
- instruction 1 is the QUAD READ. same here.
- I tried to add several read/write instruction in a LUT sequence but couldnt make it work. Is it possible ? Can the AHB controller read AND write during the same sequence ?
I need to optimize speedrate :
- I reduced spacing between data burst by configuring FLSHA1CR1. It seems that the minimal value is around 6 SCLK cycles.
- I try to increase data size of READ and WRITE cmd. I cannot send / receive more than 16 bytes at each cmd :
- changing the size in the LUT operand has no impact
- adding a LUT_DATSZ_SDR instruction has no impact
- enable prefetch lengthens the read burst to 4096 bytes. It very long ! Can it be reduced to a specified size ?
- the AHB TX may be limiting the write burst length but It should be 64 bytes according to documentation. Is it correct on the IMX8MM ?
Any comment on this ? How can I optimize data transfer rate ?
