clko2 output problem on IMX8MQuad EVK board

[coindu]

Hi   All:

        how to use CLKO2 to ouput 24MHZ clock？

        in clk-imx8mq.c file can find CLKO2 parents input 

         static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out","video_pll1_out", "ckil", };

      when I use sys_pll_200m as clko2`s parent and set clock-rate to  24000000, the result mclk_clock will be 25M

pinctrl-0 = <&pinctrl_csi1>;
clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
<&clk IMX8MQ_CLK_CLKO2_DIV>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <0>, <24000000>;
csi_id = <0>;

      use sys_pill_166m as clko2`s parent ,  the result csi_mclk will be 23.8M

      please tell me show to ouput 24M precise with clko2

thanks

[coindu]

Thanks a lot.  

[igorpadykov]

Hi coin

to ouput 24M precise with clko2 you should select appropriate parent clock

source which could be evenly (precisely) divided, probably reprogramming some plls.

For example sys_pill_166m can not be divided by some integer to get 24M, most close

divider 7 will give the result 23.8M.

Best regards
igor
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