I ask because of an SGI problem I;m having with the Freescale Platform SDK and the GIC unit test. The processor never gets to the registered interrupt service routine. The interrupt is triggered and even acknowledged.
It is OK for this register's value being 001 even on a Solo. The CPU interface means, this is a private interface for each core, although its address is same, 0xa00100 is the GIC_CPU interface's base address, but each core will need to enable it before getting it start to work. In our v3.0.35 kernel, when booting up secondary core, arch/arm/mach-mx6/platsmp.c's platform_secondary_init will call gic_secondary_init to initialize this secondary core's GIC CPU interface.
So, in a word, GIC_DIST is common, all cores' read/write into GIC_DIST will impact same DIST interface. But for GIC_CPU interface, each core has its own interface, can only be seen/read/write by its core.
On your solo, as only CPU0's GIC_CPU interface is initialized, so it is OK. I think this register can NOT be set in runtime, it is a fixed value by hardware design.