Why does 16-channel capture require 3072fs MCLK in TDM mode

[eSonarOpenSourceSM2]

In order to access 16 channels at 32-bit on SA1 of a Coral Dev board, I'm being forced to set the PLL frequency to 24576000Hz (MCLK master frequency), but my ADC chip requires 8192000Hz (TDM1024fs based on 8000Hz sampling). 

I'll provide the device tree for discussion purposes as needed.

[JorgeCas]

Hello,

It seems that your design PLL/prescaler needs that clock rate to play audio in your required sample rate.

Best regards.

[eSonarOpenSourceSM2]

The device-tree and its settings are wonderfully flexible but it leads to a sense of black-magic. 

I don't have immediate access to my specific device tree, but the idea is similar to https://community.nxp.com/t5/i-MX-Processors/How-to-specifiy-clocks-for-SAI-in-device-tree/td-p/1155... and specifically setting IMX8MM_AUDIO_PLL1_OUT to <24576000>.  Again this is all black magic (if there's a guide to all these register values I'd love to know where it is). 

Here's what I want: Ideally I'd like the IMX8MM_AUDIO_PLL1_OUT to always operate in TDM512 or TDM1024 compatible with either the simple_audio_card driver or the ak5558 codec module (the latter is co-written by  <mihai.serban@nxp.com>). The sample frequencies I need are 8kHz or 16kHz, so the MCLK should automagically set itself to 512x or 1024x the sample rate. 

Here's what I get: When successful, the recording is done using Python and portaudio/pyaudio and the frequencies seem to set themselves given the number of channels, bit-depth and sample rate. In the event that the device tree settings are incompatible, Python reports an "unanticipated hardware error".

[JorgeCas]

Hello,

Our BSP works with 12288000 and 24576000, that is the default configuration for clock driver to derivate required playback frequencies.

Best regards