Why are pad controls for LCD pins 0x10 (invalid speed field)?

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Why are pad controls for LCD pins 0x10 (invalid speed field)?

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ThomasG1z
Contributor III

I see in e.g. the devicetree files for e.g. the SabreSD or Nitrogen6x that the pad control for all the relevant pins for the LCD parallel interface are set to 0x10. Why is that? It means that the SPEED field is set to 00 which is reserved according to the reference manual. Is there a particular reason, something I've overlooked or just an error..?

pinctrl_ipu1: ipu1grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10

...

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igorpadykov
NXP Employee
NXP Employee

yes, pad controls of the Dual/Quad are similar to Solo/Duallite

and next Solo/Duallite RM will be updated with this info.

~igor

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782件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

Hi ThomasG1z

setting Speed 00 LOW — Low frequency (50 MHz)

according to i.MX6DQ RM

MX6DQRM  rev.2  7_2014     p.2290.jpg

Best regards

igor

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ThomasG1z
Contributor III

I see now that the documentation has been changed from the 2013 to 2014 version currently listed on your site. However for the i.MX6S/DL the reference manual on your web pages are still from 2013 and the speed field is documented like this:

pastedImage_0.png

But I assume the pad controls of the Dual/Quad are similar to Solo/Duallite so this field is not really reserved??

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783件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

yes, pad controls of the Dual/Quad are similar to Solo/Duallite

and next Solo/Duallite RM will be updated with this info.

~igor

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