Where can I get BSDL-like information for the "SDMA" and "DAP_A9" units in the i.MX6Quad?

[adamley]

Figure 56-2 in "IMX6DQRM" shows SJC, SDMA and DAP_A9 units in the MOD=0 chain, as follows

Note that DAP_M4 also appears, but I presume this is spurious and i.MX6Q does not have a Cortex-M4 core as far as I know ...

The BSDL for the SJC has been discussed and linked elsewhere in these communities, but where MOD=0 operation is desired in conventional boundary-scan tool kits, BSDL for SDMA and DAP_A9 are also required.

I can "dummy" such up myself from educated guesses that I can make, but I'd much rather have an authoritative source from the vendor.

Thanks!

#BSDL #i.MX6Quad #SDMA #DAP_A9

[adamley]

Thank you, igorpadykov‌, for your reply.

I find that I still wish for additional information, since all of the detail and references you have kindly provided were already known to me and well understood.

The minimal information required to construct the "BSDL" that I intend is as follows:

• Does the unit support the IDCODE?
  • if so, what is the binary code for IDCODE instruction and what is the 32 bit value for IDCODE_REGISTER?
• What is the INSTRUCTION_LENGTH of the unit?
• What are the valid INSTRUCTION_OPCODE of the unit?
  (all undefined codes should decode to BYPASS)
• What is the INSTRUCTION_CAPTURE of the unit?
  (bit positions that are non-deterministic should be defined as 'X')

Thanks again for your support!

[igorpadykov]

Hi Adam

one can check sect.56.5.1 ID_CODE Instruction (IDCODE)

i.MX6DQ Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

Best regards
igor

[adamley]

Thank again, Igor.

You've addressed the SJC unit, but my question pertains to the SDMA and DAP_A9 units.

I believe that I've found some useful information concerning SDMA at Sect 55.4.13.1 OnCE Commands in i.MX6DQ Reference Manual (http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf) ??

And, for the DAP_A9, I presume Sect 3.3.2 Required Instruction Register (IR) instructions of the ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 (https://static.docs.arm.com/ihi0031/c/IHI0031C_debug_interface_as.pdf) is the authoritative reference ??

[igorpadykov]

Hi Adam

additional info can be found in sect.6.4 Defining the JTAG chain

attached older revision i.MX6DQ User Guide, also from bsdl file from below link,

JTAG_MODE should be high [attribute COMPLIANCE_PATTERNS] for bsdl testing.

BSDL (2)
i.MX 6Quad and i.MX 6Dual BSDL File

i.MX6Q|i.MX 6Quad Processors|Quad Core|NXP 

Best regards
igor
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