I am using the iMX8MN DDR EVK and boot the M7 core from U-Boot using the bootaux command.
I run the M7 from DDR, it is running a simple Hello World application.
I'm able to start the M7 from DDR offsets between 0x6000.0000 and higher.
However, when using a DDR offset below 0x6000.0000, the M7 does not start. Bootaux does not report an error.
All memory ranges I have tried (including those below 0x6000.0000) are not in use by U-Boot.
I know this because through 'cmp' I see the M7 binary and reserved memory is identical in all tested memory ranges before starting the M7.
M7 linker settings and U-Boot output when using DDR offset 0x8000.0000:
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240
m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x0001FDC0
m_data (RW) : ORIGIN = 0x80020000, LENGTH = 0x00010000
m_data2 (RW) : ORIGIN = 0x80030000, LENGTH = 0x00010000
}
U-Boot:
imx=> mw 0x50000000 0xffffffff 0x40000
imx=> mw 0x80000000 0xffffffff 0x40000
imx=> tftp 0x50000000 test.bin
imx=> tftp 0x80000000 test.bin
imx=> dcache flush;
imx=> cmp 0x80000000 0x50000000 0x40000
Total of 262144 word(s) were the same
imx=> bootaux 0x80000000
## Starting auxiliary core stack = 0x80030000, pc = 0x80000305...
At this point, the M7 boots succesfully.
M7 linker settings and U-Boot output when using DDR offset 0x5000.0000:
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x50000000, LENGTH = 0x00000240
m_text (RX) : ORIGIN = 0x50000240, LENGTH = 0x0001FDC0
m_data (RW) : ORIGIN = 0x50020000, LENGTH = 0x00010000
m_data2 (RW) : ORIGIN = 0x50030000, LENGTH = 0x00010000
}
U-Boot:
imx=> mw 0x50000000 0xffffffff 0x40000
imx=> mw 0x80000000 0xffffffff 0x40000
imx=> tftp 0x80000000 test.bin
imx=> tftp 0x50000000 test.bin
imx=> dcache flush;
imx=> cmp 0x80000000 0x50000000 0x40000
Total of 262144 word(s) were the same
imx=> bootaux 0x50000000
## Starting auxiliary core stack = 0x50030000, pc = 0x50000305...
At this point, the M7 does not boot all.
Again; I can repeat this test for various offsets with the same effect: everything above 0x6000.0000 works, e.g.
0x6000.0000, 0x8000.0000, 0xa000.0000, etc.
everything below 0x6000.0000 fails, e.g.
0x5000.0000, 0x4d00.0000, etc.
I have tested this with both my own U-Boot build, and the pre-built U-Boot from L5.4.24-2.1.0_images_MX8MNEVK.
Both give the same outcome.
According to 'i.MX 8M Nano Applications Processor Reference Manual, Rev. 0, 12/2019' the DDR ranges I use are in both the M7 and A53 memory map.
Questions:
- Am I overlooking anything that could cause this?
- Are you able to run the M7 from DDR below 0x6000.0000 on your side?
