Hi,
I am using a bit of code to initialize a 2Mbyte section of memory from within the board_init function in the Cortex M4 SCU SCFW software and It works quite well. What it does is to read 32 bit data values and write them back from address 0x80000000...0x801FFFFC. In doing so it clears the designated area of any ECC errors caused by initialization of the SDRAM memory. That works perfectly as I have tested it thoroughly.
Originally I simply created a for loop in C, analysed what it looked like in assembly and stripped out whatever bits/instructions were not necessarily and it still works perfectly. When I used the C code it takes about 175 ms to complete. When I used the minimized assembly code it still takes about 168 ms.
I am not an expert on caching but a colleague is, albeit on another processor platform. So we looked things up and it appears the SCU supports using the PLD function as it supposed to have 16Kbyte instruction and data L1 caches. I have tried using the PLD function with all sorts of offsets from 16....128 but it does not make any difference at all, in spite of the fact that everything builds just fine.
. The total execution time stays at a rock solid 168 ms.So I assume I am missing something but I have not found anything in the documentation.
Is there anyone out there who can point out as to what is missing?
