UART5 pads(Pins) initialization

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UART5 pads(Pins) initialization

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mail2yangliu
Contributor II

Following the code snippet is to initialize the four pads/pins as UART5 pins, I am just wondering if there are something wrong? such as the initializing sequence for each pin, and values for the relative registers? Those that I am not quite sure are the Select Input Registers setting. Such as in lines 5 & 11,  17 & 23. I mean why the same value is used to set Select Input Register? Could please someone have a comment on this?

Thanks,

Yang

1. // Config uart5.UART5_CTS_B to pad KEY_ROW4

2. (int *)020e_0268 = 4;

3. // ENABLED, 100K_OHM_PU, PULL, ENABLED, DISABLED, 100MHZ, 40_OHM, SLOW

4. (int *)020e_0650 = 0x0001B0B0;

5. (int *)020e_0918 = 2;

6.

7. // Config uart5.UART5_RTS_B to pad KEY_COL4

8. (int *)020e_0254 = 4;

9. // ENABLED, 100K_OHM_PU, PULL, ENABLED, DISABLED, 100MHZ, 40_OHM, SLOW

10. (int *)020e_063c = 0x000130B0;

11. (int *)020e_0918 = 2;

12.

13. // Config uart5.UART5_RX_DATA to pad KEY_ROW1

14. (int *)020e_025c = 4;

15. // ENABLED, 100K_OHM_PU, PULL, ENABLED, DISABLED, 100MHZ, 40_OHM, SLOW

16. (int *)020e_0644 = 0x0001B0B0;

17. (int *)020e_091c = 3;           // KEY_ROW1_ALT4

18.

19. // Config uart5.UART5_TX_DATA to pad KEY_COL1

20. (int *)020e_0248 = 4;

21. // ENABLED, 100K_OHM_PU, PULL, ENABLED, DISABLED, 100MHZ, 40_OHM, SLOW

22. (int *)020e_0630 = 0x0001B0B0;

23. (int *)020e_091c = 3;           // KEY_ROW1_ALT4

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igorpadykov
NXP Employee
NXP Employee

Hi Yang

please look at Chapter 30 IOMUX Controller (IOMUXC)

i.MX6SL Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SLRM.pdf

Best regards

igor

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