The fec2 of the imx8qm is connected to the sja1105Q. The sja1105 is connected to four channels of phy. When the fec2 network port is initialized, mdio scans all the phys on the bus. At this time, the sja1105Q has not been initialized, so the phy mode of the phys on the mdio bus cannot be determined. As a result, the phys connected to the mdio cannot probe. so the phy cannot work normally.
Software version imx-automotive-11.0.0_ 2.5.0
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
fsl,magic-packet;
nvmem-cells = <&fec_mac1>;
nvmem-cell-names = "mac-address";
fsl,mii-exclusive;
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
fec2_ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
fec2_ethphy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x2>;
};
fec2_ethphy8: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x8>;
};
fec2_ethphy9: ethernet-phy@9 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x9>;
};
};
};
&lpspi1 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>;
cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
status = "okay";
switch: sja1105@0 {
compatible = "nxp,sja1105q";
reg = <0x0>;
reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>;
spi-max-frequency = <4000000>;
spi-cpha;
fsl,spi-cs-sck-delay = <1000>;
fsl,spi-sck-cs-delay = <1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
label = "swp0";
ethernet = <&fec2>;
phy-mode = "rgmii-id";
reg = <0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
label = "swp1";
phy-mode = "mii";
phy-handle = <&fec2_ethphy8>;
reg = <1>;
};
port@2 {
label = "swp2";
phy-mode = "mii";
phy-handle = <&fec2_ethphy9>;
reg = <2>;
};
port@3 {
label = "swp3";
phy-mode = "rgmii-id";
phy-handle = <&fec2_ethphy1>;
reg = <3>;
};
port@4 {
label = "swp4";
phy-mode = "rgmii-id";
phy-handle = <&fec2_ethphy2>;
reg = <4>;
};
};
};
};
