Stuck in Uboot after uuu flash until WDOG reboots board

[malj]

Hello,

I am working on a custom board with a imx6ull, and I had to disable the &lcdif node the uboot dts (the we have taken most of it from 6ull 14x14 evk). After doing that I got the following error:

downloading of 576551 bytes finished
writing to partition 'bootloader'
Initializing 'bootloader'
switch to partitions #1, OK
mmc1(part 1) is current device
Writing 'bootloader'

MMC write: dev # 1, block # 2, count 1127 ... 1127 blocks written: OK
Writing 'bootloader' DONE!

### NOTE: POWER CYCLE ON PSU, this is not a part of the console printout ###

U-Boot 2022.04-lf_v2022.04+g181859317b (Nov 15 2022 - 06:28:05 +0000)

CPU:   i.MX6ULL rev1.1 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 43C
Reset cause: POR
Model: Product name
Board: MX6ULL 14x14 EVK
       Watchdog enabled
DRAM:  512 MiB
Core:  65 devices, 17 uclasses, devicetree: separate
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

Fail to setup video link
In:    serial
Out:   serial
Err:   serial
switch to partitions #0, OK
mmc1(part 0) is current device
flash target is MMC:1
Net:   Could not get PHY for FEC1: addr 1
Could not get PHY for FEC1: addr 1
Get shared mii bus on ethernet@2188000
prefetch abort
pc : [<e59ff018>]          lr : [<9ff739cd>]
reloc pc : [<cd290018>]    lr : [<878049cd>]
sp : 9ef656f8  ip : 00000020     fp : 00000017
r10: 00000001  r9 : 9ef6cec0     r8 : 9ef6e4b8
r7 : 9ef6e458  r6 : 9ef70348     r5 : 00000002  r4 : 000000d0
r3 : e59ff01c  r2 : 00002820     r1 : 9ef6e458  r0 : 000000d0
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
Code: ff18f7ff f0444806 f7ff63e3 b5084604

I have noticed the following behavior:

• If I power cycle the board the issue continues to happen.
• If I wait for wdog to reboot the board, it boots normally and works as expected going forward.
• If I instead of power cycling the board after flashing and do `ctrl+c` and then type `boot` it works immediately

When debugging I added logging to uboot config by  adding following:

CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=9
CONFIG_LOG_DEFAULT_LEVEL=6
CONFIG_LOG_CONSOLE=y
CONFIG_LOGF_FILE=y
CONFIG_LOGF_FUNC=y
CONFIG_LOGF_LINE=y

CONFIG_SPL_LOG=y
CONFIG_SPL_LOG_MAX_LEVEL=9
CONFIG_SPL_LOG_CONSOLE=y

Then it started to work without issues... So I suspects it something with a timing? Then I realized that we have the "failed to setup video link" so I removed the logging again and instead added:

# CONFIG_DM_VIDEO is not set
# CONFIG_SYS_WHITE_ON_BLACK is not set
# CONFIG_VIDEO is not set
# CONFIG_SYSRESET is not set
# CONFIG_SYSRESET_WATCHDOG is not set
# CONFIG_WATCHDOG is not set
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_HW_WATCHDOG=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
# CONFIG_ULP_WATCHDOG is not set
# CONFIG_DESIGNWARE_WATCHDOG is not set
# CONFIG_WDT is not set
# CONFIG_PVBLOCK is not set
# CONFIG_PHYS_TO_BUS is not set

in an attempt to remove the video.

MMC write: dev # 1, block # 2, count 999 ... 999 blocks written: OK
Writing 'bootloader' DONE!

### NOTE: board powercycled 

U-Boot 2022.04-lf_v2022.04+g181859317b (Nov 15 2022 - 06:28:05 +0000)

CPU:   i.MX6ULL rev1.1 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 42C
Reset cause: POR
Model: Product name
Board: MX6ULL 14x14 EVK
       Watchdog enabled
DRAM:  512 MiB
Core:  65 devices, 17 uclasses, devicetree: separate
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
switch to partitions #0, OK
mmc1(part 0) is current device
flash target is MMC:1
Net:   Could not get PHY for FEC1: addr 1
Could not get PHY for FEC1: addr 1
Get shared mii bus on ethernet@2188000
undefined instruction
pc : [<00000358>]          lr : [<9ff9fb6b>]
reloc pc : [<e7881358>]    lr : [<87820b6b>]
sp : 9ef756e8  ip : 00000020     fp : 00000017
r10: 00000001  r9 : 9ef7cec0     r8 : 9ef7e4b8
r7 : 9ef7e458  r6 : 00000006     r5 : 00000004  r4 : 9ef7f660
r3 : 00000358  r2 : 00000006     r1 : 00000004  r0 : 9ef7f660
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Code: f4435340 61935380 f4236993 61931380 (f0436953)
Resetting CPU ...

resetting ...


U-Boot 2022.04-lf_v2022.04+g181859317b (Nov 15 2022 - 06:28:05 +0000)

CPU:   i.MX6ULL rev1.1 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 43C
Reset cause: POR

and it boots fine. On a power cycle it happens again but on a soft reset it boots without the uboot resetting.

I want to understand what is at play and how the behaviour can be explained.

[Zhiming_Liu]

Hi @malj 

You can try to remove the lcd code cleanly, remove setup_lcd function in board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c

void board_quiesce_devices(void)
{
#if defined(CONFIG_VIDEO_MXS)
	enable_lcdif_clock(LCDIF1_BASE_ADDR, 0);
#endif
}

And the ethernet error log could also be a suspect location, you can try to disable them if you still face this issue after you remove all code about lcdif.