How to setup EIM on iMX7 to emulate legacy INTEL bus

[mario_stefani]

Dear Mr Yuri Thanks for the help.

We had use the references mentioned and the bus is not working as expected. Read bus access is always with page mode access, even when explicitly defined by APR , DSZ set in 32 bits

We used the following register settings

EIM_CS0GCR1 = 0x07f35C39

EIM_CS0GCR2 = 0x00001002

EIM_CS0RCR1 = 0x08222222

EIM_CS0RCR2 = 0x00000000

EIM_CS0WCR1 = 0x08249259

EIM_CS0WCR2 = 0x00000000

EIM_WCR = 0x00000809

We explicit defined bus asynchronous page read APR=0 on CS0RCR2 field, and the bus continues to show eight access cycles every read .

Are there any other register to set it?

Thanks!

[Ilan_Figueiredo]

Hello @Yuri ,

By using EIM_CS0GCR1 = 0x07f35C3D (EIM_CSGCR1_SRD enabled) we got the following in the logic analyzer:

The Write is done without issues, in a single cycle. The Read, however, is done twice. The software in M4 gets the first value collected.

I am working along Mario to solve this issue.