Hi,
i've some questions regarding to HW_CLKCTRL_SSPx on the i.MX28, which are not really clear from the reference manual:
What are the exact consequences of changing DIV_FRAC_EN?
Is it necessary to check BUSY or CLKGATE before changing DIV_FRAC_EN?
What does it mean to the DIV field if DIV_FRAC_EN=1?
Is there a relation / constraint between HW_CLKCTRL_SSPx.DIV_FRAC_EN and HW_CLKCTRL_CLKSEQ.BYPASS_SSPx?
Best regards
Stefan Wahren
Solved! Go to Solution.
Hi Stefan
DIV_FRAC_EN enables fractional divider, this is described in
i.MX28 Reference Manual sect.10.3.2 Fractional Clock Divide Mode
http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf
>Is it necessary to check BUSY or CLKGATE before changing DIV_FRAC_EN?
yes
>Is there a relation / constraint between HW_CLKCTRL_SSPx.DIV_FRAC_EN
>and HW_CLKCTRL_CLKSEQ.BYPASS_SSPx?
no, this bit allows to switch to XTAL as clock source for SSP. Please check
description in sect.10.8.26:
"PLL0 and 9-phase fractional divider must already be configured when
this bit is cleared."
Best regards
igor
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Hi Stefan
DIV_FRAC_EN enables fractional divider, this is described in
i.MX28 Reference Manual sect.10.3.2 Fractional Clock Divide Mode
http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf
>Is it necessary to check BUSY or CLKGATE before changing DIV_FRAC_EN?
yes
>Is there a relation / constraint between HW_CLKCTRL_SSPx.DIV_FRAC_EN
>and HW_CLKCTRL_CLKSEQ.BYPASS_SSPx?
no, this bit allows to switch to XTAL as clock source for SSP. Please check
description in sect.10.8.26:
"PLL0 and 9-phase fractional divider must already be configured when
this bit is cleared."
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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