Question about FREQ1/2 setpoint Clock Cycle Freq of DDR Register Programming Aid

[ko-hey]

Hi all,

I have a question about FREQ1/2 setpoint Clock Cycle Freq of DDR Register Programming Aid which can be downloaded from following link.

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8MNano-m815S-DDR-Register-Programmin...

According to description for sheet, the settings are fixed as below in the sheet.

I wondered if FREQ1 and FREQ2 depend on frequency rather than fixed values.

Q1.

What is this value (200MHz, 50MHz) based on?

Q2.

Can you tell me why this value can be a fixed value?

Ko-hey

[Yuri]

@ko-hey 
Hello,

   Those working points are used by NXP Linux with CPUFREQ and Dynamic
Bus Frequency features.

Regards,
Yuri.

[ko-hey]

@Yuri 

Thank you for reply.

Which source code does the setpoint use ?

Is it recommended to use it unchanged ?

Ko-hey

[Yuri · Accepted solution]

@ko-hey 

  Look at section " Dynamic Bus Frequency" in "i.MX_Reference_Manual.pdf".

Yes, it may be recommended to not modify it.

~Yuri.

[ko-hey]

@Yuri 

According to Table 16. BusFrequency Set Points, i.MX 8M had a DDRC APB clock of 200MHz.
FREQ1 setpoint Clock cycle Freq (C31 cell, 200MHz) in the Register Configuration sheet refers to the DDRC APB clock.
Is my understanding correct?

On the other hand, the clock corresponding to FREQ2 setpoint clock cycle freq (C33 cell, 50MHz) was not described in the above pdf.
Which clock does the 50MHz clock refer to ?

ko-hey

[Yuri]

@ko-hey 
Hello,

  "Although there are three frequency points in the BSP and RPA tool including ~1500MHz/200MHz/50MHz, we only use the highest frequency  and the lowest frequency 50MHz(FREQ2) in the BSP."

Regards,
Yuri.

[ko-hey]

@Yuri 

Could you answer the above my question ?

Ko-hey