MIPI CSI and IPU questions

[kristofferglemb]

Hi,

I have some questions regarding MIPI CSI and IPU on the IMX6Q.

1.

In the following thread Some Experience When Enable MIPI Camera it is stated that you need to set the MIPI DPHY clock by writing to MIPI_CSI2_PHY_TST_CTRL1. Where can I find the documentation explaining how to properly initialise the DPHY?

2.

For a MIPI V4L2 camera driver, how should the ifparm struct be set up in the g_ifparm ioctl, e.g. if_type, clock_curr/min/max?

3.

It is stated in the IPU documentation that it has a maximum frame size of 8Kx4K. Does this apply even if want to store a captured image directly to memory or can I capture larger images?

Best regards,

Kristoffer

[Yuri]

  The stage of D-PHY initialization includes an access the D-PHY programming interface
to initialize and program the D-PHY according to the selected operating mode of the D-PHY.
This is D-PHY dependent, and this programming should be carried out according to the DPHY
databook. Sorry, there is no detailed information about programming internal MIPI CSI-2

DPHY registers (because of third party agreement.), that may be done via the MIPI_CSI_PHY_TST_CTRL0/1
registers. Some descriptions may be found regarding corresponding test registers of MIPI DSI DPHY.
Please take a look at section 41.5.1 (DSI and D-PHY initialization sequence) of the i.MX6 DQ RM. 
An example also may  be found in  C-function "mipi_csi2_controller_program" from the Platform SDK.
Generally it may be recommended to follow FSL BSP settings.

   As for IPU frame size (up to 8192 x 4096) – it should be considered as internal restriction of the IPU.

Have a great day,
Yuri

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[kristofferglemb]

Hi Yuri,

Both you and the reference manual refer to the DPHY databook which you cannot give out due to third party license agreement. At least then I think you must be able to answer if there is something I need to change in the initialisation depending on e.g. DPHY clock frequency. It seems like that in the thread I referenced. If I use a DPHY lane frequency of 400 MHz what should be written to the DPHY internal register?

Regarding resolution, what parts of the IPU are restricted? Seems to me that at least the CSI -> MEM path should be able to cope with any resolution. Is it dependant on CSI2 datatype?

Best regards,

Kristoffer

[ludovicleau-mer]

Hi Kristoffer,

for configuring the dphy lane frequency you can modify the register in file :

driver/mxc/mipi/mxc_mipi_csi2.c

int mipi_csi2_reset(struct mipi_csi2_info *info)

for my custom camera i use several lane frequency so i rewrite the mipicsi2_reset to modify like :

			/* phy_testclr = 1 (0b01) test interface clear */
			mipi_csi2_write(info, 0x00000001, MIPI_CSI2_PHY_TST_CTRL0);
			/* phy_testdin (0) test interface input */
			mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL1);
			/* 32'h00000000 this disables the testclr pin
			enabling the interface to write new values to the DPHY internal registers. */
			mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);
			/* phy_testclk = 1 (0b10) test interface strobe signal
			use to clock TESTDIN bus into D-PHY */
			mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);
			/* phy_testen (1) configure address write operation of TESTCLK
			phy_testdin (0x44) register address */
			mipi_csi2_write(info, 0x00010044, MIPI_CSI2_PHY_TST_CTRL1);
			mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);
			/* change clock */
			mipi_csi2_write(info, clockreg << 1, MIPI_CSI2_PHY_TST_CTRL1);
			/* phy_testclk = 1 (0b10) test interface strobe signal
			use to clock TESTDIN bus into D-PHY */
			mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);
			mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);

with clockreg the good value for register like 0x06 for 400 to 450 MHz.

regards

[wallyyeh]

sorry, but I wanna ask a dumb question:

/* change clock */

mipi_csi_write(info, clockreg << 1, MIPI_CSI_PHY_TST_CTRL1);

what does this clock mean? frequency of MIPI data lane?

I also got entire list about frequencies - values mapping table, might be useful if someone need:

//  950-1000MHz :0x74   //999Mhz

//  900-950Mhz  :0x54   //972Mhz

//  850-900Mhz  :0x34   //900Mhz

//  800-850MHz  :0x14   //849Mhz

//  750-800MHz  :0x32   //783Mhz

//  700-750Mhz  :0x12   //750Mzh

//  650-700Mhz  :0x30   //699Mhz

//  600-650MHz  :0x10   //648Mhz

//  550-600MHz  :0x2e   //600Mhz

//  500-550Mhz  :0x0e   //549Mhz

//  450-500Mhz  :0x2c   //486Mhz

//  400-450MHz  :0x0c   //450Mhz

//  360-400MHz  :0x4a   //399Mhz

//  330-360Mhz  :0x2a   //360Mhz

//  300-330Mhz  :0x48   //330Mhz

//  270-300MHz  :0x28   //300Mhz

//  250-270MHz  :0x08   //270Mhz

//  240-250Mhz  :0x46   //249Mhz

//  210-240Mhz  :0x26   //240Mhz

//  200-210MHz  :0x06   //210Mhz

//  180-200MHz  :0x44   //198Mhz

//  160-180Mhz  :0x24   //180Mhz

//  150-160MHz  :0x04   //159Mhz

//  140-150MHz  :0x42   //150Mhz

//  125-140MHz  :0x22   //135Mhz

//  110-125MHz  :0x02   //123Mhz

//  100-110Mhz  :0x40   //108Mhz

//  90-100Mhz   :0x20   //99Mhz

//  80-90Mhz    :0x00   //90Mhz (default)

Wally

[wallyyeh]

Ok, I got it. this clock means your mipi data lane's frequency which SOC expected from mipi device, must match! or you will never get the correct data from SOC(I use i.MX6DL).

and device's mipi data lane freq always twice than mipi clock lane's freq. because mipi using DDR mode to transfer data.