LPSPI configuration questions regarding the PCS and HREQ

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LPSPI configuration questions regarding the PCS and HREQ

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msaliharslan
Contributor III

Hi, I have a MXRT1052 on a custom board and I need to communicate with AD7175-8 ADCs via SPI. There are four ADCs on the board three of which are connected to LPSPI1 and one of them is connected to LPSPI1. CPU is the SPI master. As stated in the data sheet of AD7175-8, it takes the MISO to low if PCS is zero. I want to use this signal as an interrupt to read data. However, in order to do this PCS pins must be kept low which as far as I understand is not possible with LPSPI functioning. I thought instead of routing those pins to PCSs of SPI, assigning them as GPIO and manually writing to the pins. Since there are more than one slave while communicating with one of them, pins connected to the others must be kept high. My question is if none of the PCS pins are routed to SPI, would there be any problem in SPI functioning?

Also, another question that is it even possible detect an interrupt in SDI pin of SPI module. In reference manual it says that when HRSEL is set to 1, "Host request input is the input trigger", but I am not sure what this means.

Lastly, does SPI in master mode generates clock signal as an output while not communicating?

Thanks in advance.

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hello Salih,

 

The LPSPI module is capable of changing the PCS polarity using CFGR1[PCSPOL] register, this way you can adapt the SPI communication according to your device needs. I recommend you to check chapter 42.4.1.9 of the reference manual for more information.

 

Hope it helps!

 

Best regards,

Felipe

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msaliharslan
Contributor III

Let me clarify, as far as I understand LPSPI module activates PCS pins (Low or high depending on  CFGR1[PCSPOL]) while data transmission is on going. However, what I need is that all PCS pins to be active while there is no transmission and one of them to stay active whereas all the others to become deactivated just before the start of a transmission. Changing CFGR1[PCSPOL] before the transmission results in this way, but in reference manual it says "The CFGR1 should only be written when the LPSPI is disabled." So, does

         Disable LPSPI

         Change CFGR1[PCSPOL]

         Enable LPSPI

work or disabling and enabling cause problems? As an alternative, does rest of the LPSPI module works normally if I define all PCS pins as GPIO and control them outside of the LPSPI?

When both CFGR0[HREN] & CFGR0[HRSEL] are set to 1 what happens? where and how the input trigger is received?

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hello Salih,

 

Enabling and disabling LPSPI module should not cause any problems. However, you have to make sure there is no transmission occurring or you will lose information. In case you want to use CS as GPIO you will have to manage assertion and desertion of the pins by yourself.

 

Regarding your second question, when HRSEL=1 input trigger is selected. If you are using this option you will need to configure input trigger by using XBARA module.

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Hope it helps!

 

Best regards,

Felipe