LPDDR2 suspend on imx6sll

Showing results for 
Search instead for 
Did you mean: 

LPDDR2 suspend on imx6sll

Contributor I

Hello all,

In order to add self-refresh support to lpddr2 on imx6sll, I created two arrays of offset for "mmdc io" and "mmdc" in the file "pm-imx6.c" but I can not figure out which registers I need to specify for "mmdc io offset" and "mmdc offset". And what configurations should be specified for "mmdc offset" registers.

Maybe there is some example of how to do it?

Labels (2)
Tags (2)
2 Replies

NXP TechSupport
NXP TechSupport

Hi Valentin

one can look at MMDC baremetal examples in SDK, it (1.1.0_iMX6_Platform_SDK.zip)

can be found on  SMP Enable in IMX6 

Best regards
Note: If this post answers your question, please click the Correct Answer button. Thank you!

0 Kudos

Contributor I

Hi Igor,
Thank you for your reply.

I have an example of the registers "mmdc io offset" and "mmdc offset" for imx6sx :
static const u32 imx6sx_mmdc_io_lpddr2_offset[] __initconst = {
    0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
    0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
    0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
    0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
    0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
    0x324, 0x328, 0x340,        /* DRAM_SDCKE0 ~ 1, DRAM_RESET */

static const u32 imx6sx_mmdc_lpddr2_offset[] __initconst = {
    0x01c, 0x85c, 0x800, 0x890, /*MDSCR,MPZQLP2CTL,MPZQHWCTRL,MPPDCMPR2*/
    0x8b8, 0x81c, 0x820, 0x824, /*MPMUR0,MPRDDQBY0DL,MPRDDQBY1DL,MPRDDQBY2DL*/
    0x828, 0x82c, 0x830, 0x834, /*MPRDDQBY3DL,MPWRDQBY0DL,MPWRDQBY1DL,MPWRDQBY2DL*/
    0x838, 0x848, 0x850, 0x8c0, /*MPWRDQBY3DL,MPRDDLCTL,MPWRDLCTL,MPDCCR*/
    0x83c, 0x840, 0x8b8, 0x00c, /*MPDGCTRL0,MPDGCTRL1,MPMUR0,MDCFG0*/
    0x004, 0x010, 0x014, 0x018, /*MDPDC,MDCFG1,MDCFG2,MDMISC*/
    0x02c, 0x030, 0x038, 0x008, /*MDRWD,MDOR,MDCFG3LP,MDOTC*/
    0x040, 0x000, 0x020, 0x818, /*MDASP,MDCTL,MDREF,MPODTCTRL*/
    0x800, 0x004, 0x01c,        /*MPZQHWCTRL,MDPDC,MDSCR*/

And the configuration for some registers "mmdc offset":

if (cpu_is_imx6sll() &&
        pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) {
        pm_info->mmdc_val[0][1] = 0x8000;
        pm_info->mmdc_val[2][1] = 0xa1390003;
        pm_info->mmdc_val[3][1] = 0x400000;
        pm_info->mmdc_val[4][1] = 0x800;
        pm_info->mmdc_val[18][1] = 0x800;
        pm_info->mmdc_val[20][1] = 0x20024;
        pm_info->mmdc_val[23][1] = 0x1748;
        pm_info->mmdc_val[32][1] = 0xa1310003;

I'm trying to figure out why they are installed, in order to understand what registers I need to set up for me for imx6sll.

Best regards

0 Kudos