LDO turning from 0x1F to 0x1E cause i.MX6DL hang

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LDO turning from 0x1F to 0x1E cause i.MX6DL hang

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norishinozaki
Contributor V

Hello Champs,

My customer encountered a CPU hang when going to analog bypass mode(0x1E) from LDO bypass mode(0x1F).

1

-  CPU=396MHz, PMIC-ARMCORE(SW1A/B)=1.3V

-  PMU_REG_CORE-REG0_TARG4–0)= 10010(1.150V:LDO Enable )

2-1

-  CPU=396MHz, PMIC-ARMCORE(SW1A/B)=1.3V

-  PMU_REG_CORE-REG0_TARG(4–0)= 11111(0x1F:LDO Bypass )

3

-  CPU=396MHz, PMIC-ARMCORE(SW1A/B)=1.3V

-  PMU_REG_CORE-REG0_TARG(4–0)= 11110(0x1E:Analog Bypass )

However, when they add an intermediate step 2-2 below,  they can move to analog bypass

1

-  CPU=396MHz, PMIC-ARMCORE(SW1A/B)=1.3V

-  PMU_REG_CORE-REG0_TARG(4–0)= 10010 (1.150V, LDO Enable )

2-1

-  CPU=396MHz, PMIC-ARMCORE(SW1A/B)=1.3V

-  PMU_REG_CORE-REG0_TARG(4–0)= 11111 (0x1F:LDO Bypass )

2-2

-  CPU=396MHz, PMIC-ARMCORE(SW1A/B)=1.3V

-  PMU_REG_CORE-REG0_TARG(4–0)= 11100 (1.425V, LDO Enable ) <-1.425V is out of spec, but it works fine moving to 0x1E

3

-  CPU=396MHz, PMIC-ARMCORE(SW1A/B)=1.3V

-  PMU_REG_CORE-REG0_TARG(4–0)= 11110 (0x1E:Analog Bypass )

The issue seems to relate to ERR005852, however they are not using DSM anyway.

Do you find anything wrong with the first sequence?

Best regards,

Nori Shinozaki

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norishinozaki
Contributor V

Igor,

My customer set REG0_STEP_TIME=11, but CPU hangs as well.

Remember, 0x1F => 0x1D => 0x1E doens't cause to hang CPU.

0x1F=>0x1E causes this issue.

Do you find any differences?

The customer would like to the "0x1E" so called "analog bypass mode".

What is difference between nomal bypass(0x1F) and analog bypass(0x1E)?

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

nomal bypass when LDO is shorted,

"analog bypass" is LDO in normal mode,

but since in your case output voltage is set greater than input,

LDO transistor is fully "closed", that is its resistance

is very small.

Best regards

igor

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norishinozaki
Contributor V

Igor,

> "analog bypass" is LDO in normal mode,

Does this "nomal mode" mean "ragurator mode"?

If so why this "analog bypass" is named specific to 0x1E.

My customer is really linking to know about "analog bypass mode"

Also LDO output's max value is 1.3V.

Why 1.45V(0x1E) can be allowed to set?

Is't there an issue when they set over 1.3V?

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

please look at your first post above:

"CPU=396MHz, PMIC-ARMCORE(SW1A/B)=1.3V"

according to RM REG0_TARG description

REG0_TARG= 11110 Target core voltage = 1.450V

so you are trying to set output voltage higher than input.

LDO output transistor become fully "closed" (resistance = 0)

This so called "analog bypass mode" is the same as setting

REG0_TARG=11111 Power FET switched full on. No regulation.

Actually when setting of output voltage higher than input, LDO

always will go to regim when "Power FET switched full on".

Max. VDD_ARM_CAP = 1.3V according to datasheet IMX6SDLCEC

Table 7. Absolute Maximum Ratings.

~igor

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norishinozaki
Contributor V

Igor,

I have to come back to this stage.

The customer is using DSM and never setting VDD_ARM_CAP values above datasheet.

They are just setting 0x1F and 0x1E as explained in ERR005852.

You once wrote "analog bypass is LDO in normal mode".

The customer is asking why this normal regulator value is allowed to be used despite the value exceeeds VDD_ARM_CAP spec in datasheet.

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

description of ERR005852 never mentions that

"regulator .. value exceeeds VDD_ARM_CAP"

Best regards

igor

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norishinozaki
Contributor V

Igor,

Thank you!

ERR005852 says "to switch to analog bypass mode (0x1E)".

You once wrote "analog bypass is LDO in normal mode", then the 0x1E is a value exceeeds VDD_ARM_CAP.

Am I messing something?

Or you mean, we can ignore datasheet in order for a workaround of the errata?

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

I think I never said that. In any case VDD_ARM_CAP

datasheet requierements should not be violated.

Best regards

igor

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norishinozaki
Contributor V

Hello Igor,

So the analog bypass mode "0x1E" is not a regulater value for LDO, it's a special value like a bypass mode "0x1F".

Correct?

The customer is wondering, what is the original purpose of the analog bypass mode "0x1E"?

Because it came out suddenly with ERR005852.

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

actually I think it is better to forget about

word "analog bypass mode" and use just word "setting 0x1E".

Then ERR005852 will be clearer for understanding:

" Workarounds:

The software workaround to prevent this issue it to switch to LDO regulator setting 0x1E, prior to

entering DSM, and then, revert to the normal bypass mode, when exiting from DSM."

Best regards

igor

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norishinozaki
Contributor V

Igor,

Thank you, let's forget it.

However the customer clings to what "0x1E" is.

Could you explain the differences between "0x1E" and "0x1F"?

I mean it's NOT the difference that 0x1F is for bypass LDO, 0x1E is for preventing VDD_ARM_CAP from slow rising after DSM.

The customer is requesting the physical or logical differences between them.

You explained me about 0x1F makes the LDO switch full-on and the dropout voltage becomes almost 0V, which causes VDD_ARM_CAP to rise slowly.

However, why 0x1E can prevent from this phenomenon?

Remember 0x1E is not a relurator value, it's a some kind of "special" value, that is what the costomer would like to know.

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

as was answered before, for ERR005852 discussion I would suggest to create new thread.

Best regards

igor

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

yes ok .

Best regards

igor

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norishinozaki
Contributor V

Hi Igor,

Is it Ok continuing it in a thread,  ERR005852 : what is "analog bypass mode"?

Best regards,

Nori Shinozaki

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norishinozaki
Contributor V

Hello Igor,

>REG0_TARG= 11110 Target core voltage = 1.450V

>so you are trying to set output voltage higher than input.

Yes, however ERR005852 says,

"The software workaround to prevent this issue is to switch to analog bypass mode (0x1E), prior to..."

You know, 11110 = 1.450V = 0x1E = analog bypass mode (= normal mode)

This errata is for entering to DSM though, there should be cases where an output voltage becomes higher than input even when DSM.

No?

Or it's allowed to set more than input voltage in DSM?

I'm confused on someting or anything?

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

I think ERR005852 is not applicable to your case since

you are not using DSM mode.

In your case one can use any *** bypass mode, just add

delay (find it experimentally) and live with it.

For ERR005852 discussion I would suggest to create new thread.

Best regards

igor

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norishinozaki
Contributor V

Hello Igor,

> I think ERR005852 is not applicable to your case since you are not using DSM mode.

Yes.

>In your case one can use any *** bypass mode, just add delay (find it experimentally) and live with it.

They did add delay(max=11) but they don't live with it unfortulately.

Any more or less, Datasheet says max VDD_ARM_CAP is 1.3V, so they can't set any regulation values exceed 1.3V(0x18) EXCEPT ***bypass mode(0x1E & 0x1F).

Is this correct?

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

yes, in any case max VDD_ARM_CAP defined by datasheet

can not be exceeded.

Best regards

igor

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norishinozaki
Contributor V

Igor,

Double check:

>yes, in any case max VDD_ARM_CAP defined by datasheet can not be exceeded.

However in any cases, setting 0x1F is allowed to turn on normal bypass mode, and 0x1E is allowed for workaround for ERR005852 when in DSM.

Is this correct understanding?

Best regards,

Nori Shinozaki

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igorpadykov
NXP Employee
NXP Employee

Hi Nori

for workaround for ERR005852 when in DSM max VDD_ARM_CAP defined by datasheet

can not be exceeded.

Best regards

igor

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