Is address incremented when using i.MX6SDL EIM continuous BCLK?

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Is address incremented when using i.MX6SDL EIM continuous BCLK?

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829件の閲覧回数
satoshishimoda
Senior Contributor I

Hi community,

Our customer have a question about i.MX6SDL EIM.

They consider using EIM continuous BCLK, but didn't understand whether address is incremented when using continuous BCLK.

Would you let me know it?

Best Regards,

Satoshi Shimoda

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659件の閲覧回数
Yuri
NXP Employee
NXP Employee

Hello,

  In synchronous mode, after address assertion, a burst of sequential

data can be accessed, assuming address incrementing is provided

by an external device (internally). Start address of the burst is provided
by i.MX6 master. Burst length is configured in EIM. From section 22.5.4
(Burst Mode (Synchronous) Memory Operation) of the i.MX6 S/DL RM :

“When this mode is set, the controller attempts to translate the Master burst
accesses to memory burst accesses, being limited by the memory burst length,
predefined by BL value, or memory and Master WRAP/INCR boundary crossing
non-matching. Only the first address accessed is put by the controller on the external
address bus in a memory burst sequence.”

  The continuous mode is differ from single burst in such manner that

the clock is not stopped right after burst finish.

Have a great day,
Yuri

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660件の閲覧回数
Yuri
NXP Employee
NXP Employee

Hello,

  In synchronous mode, after address assertion, a burst of sequential

data can be accessed, assuming address incrementing is provided

by an external device (internally). Start address of the burst is provided
by i.MX6 master. Burst length is configured in EIM. From section 22.5.4
(Burst Mode (Synchronous) Memory Operation) of the i.MX6 S/DL RM :

“When this mode is set, the controller attempts to translate the Master burst
accesses to memory burst accesses, being limited by the memory burst length,
predefined by BL value, or memory and Master WRAP/INCR boundary crossing
non-matching. Only the first address accessed is put by the controller on the external
address bus in a memory burst sequence.”

  The continuous mode is differ from single burst in such manner that

the clock is not stopped right after burst finish.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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659件の閲覧回数
satoshishimoda
Senior Contributor I

Dear Yuri,

Thank you for your reply.

According to your reply, the address signal from i.MX6 is not incremented, so external device have to increment internally by its own, right?

Best Regards,

Satoshi Shimoda

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659件の閲覧回数
Yuri
NXP Employee
NXP Employee

Hello,

> the address signal from i.MX6 is not incremented, so external device
> have to increment internally by its own, right?

Correct.

Regards,

Yuri.

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