IPU_DI Sync signals and DI#_PIN# problem

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IPU_DI Sync signals and DI#_PIN# problem

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JohnHuang
Contributor I

Dear all,

Could someone explain the DI_PIN# setting? I have checked the Reference Manual but there is no any explanation about how to set DI_PIN#. My question is

1/ Can I set HSYNC/VSYNC/BLANK signals to any DI#_PIN#?

2/ What registers handle those signals map to DI#_PIN#?

Best regards,

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bikenomad
Contributor III

The BSP provided by Freescale, for example, already defines the HSYNC signal under counter DI0_PIN2.

That's the internal HSYNC, not the external sync signal. If you're using the VGA like I'm trying to do, you need an additional pair of external sync signals.

So, yes you can assign HSYNCH to any DI#_PIN# in the driver, and then select the appropriate mux pin option for the new pin you wish to use.

It's not quite that simple. For one thing, you are limited as to which counters can drive other counters (counters can be driven only from lower-numbered counters).

Another problem is that the microcode in the controller has to be consistent with your choice of sync pins.

And the IPU section of the manual is not exactly a model of clear writing (to the point where the author of the Linux kernel driver for the display section of this chip said that he didn't think anyone could write a driver with just the RM and datasheet as references).

I've been trying to get more information on how to move the external SYNC signals for VGA to other pins and still haven't gotten it working.

For more discussion, see:

One discussion here

and:

Another discussion here

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TheAdmiral
NXP Employee
NXP Employee

Section 45.4.10.3 of the Reference Manual (IMX53RM) discusses how LCD clock signals are generated.

Basically, you have to define the clock signal in the software driver and assign it to one of eight available counters (Counter #9 is special, and does not get defined indepently). These counters are labeled DIx_PINy where x is the DI interface used (0,1) and y is the counter # (1-8). The BSP provided by Freescale, for example, already defines the HSYNC signal under counter DI0_PIN2.

 

To ouput these signals, you need to select the appropriate IOMUX pin option to output the defined counter. For example DI0_PIN2 is the ALT0 option for pin DI0_PIN2, while counter DI0-PIN7 is the ALT2 mux option for pin EIM_D18.

 

Chapter 4 of the Reference Manual maps out the Available pin muxing options and Chapter 43 contains all the register definitions to define mux assignments.

 

So, yes you can assign HSYNCH to any DI#_PIN# in the driver, and then select the appropriate mux pin option for the new pin you wish to use.

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mugheesahmed
Contributor II

Hi,

How can we assign DRDY Pin15 to any counter since there is obviously no counter number 15?

Thanks

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fei_liu
NXP Employee
NXP Employee

Hi, John,

You could see the file MX53UG.pdf  page 206 

The IPU provides the flexibility to select from a range of pins to use as an output for the synchronization
signals. Therefore, there is no unique pin for VSYNC, HSYNC and DE. However, the i.MX53 reference
boards have been assigned a specific pin for each signal, which is reflected in the schematics and BSP
support.

The default assignment is :

DI0_PIN2  HSYNC

DI0_PIN3  VSYNC

DI0_PIN15  DRDY

 

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