IMX8MN notify M7 when A53 goes to sleep (ATF GIR)

[k_specka]

Hello,
actual I'm using rpmsg from A53 to M7 as a watchdog to see if it is running.
With it sleep and wakeup is working fine. (Using the 24MHz clock on M7 to get it running in standby))

In AN13400 there is some code to notify the M Core in case A53 is going to sleep.
imx_notify_m4_set_db / imx_notify_m4_clear_db(void)

The Problem is that there is no file given where it needs to be added and I can't find it in the ATF code (so it seems that it still needs this patch)

So my question is: What is needed to notify the M core when A core is going to sleep.
Is there a patch available? Which file needs the change?

And is it possible to check from the M core if the A core is sleeping without using the notification?

[brian14]

Hi @k_specka, 

Please have a look at this thread to implement it on the iMX8MN.
Solved: imx8mm: Wake Linux from M4 core - NXP Community

Have a great day!

[k_specka]

I already have seen this thread, but it is mostly about sending the mu interrupt from M4 to A53 to wake it up.
What I am searching is the interrupt from A53 to M4 (or M7 in my case) to notify the M core about A core is going to suspend.

What I have seen now is the MU base adress which is set in the imx8mn.dtsi

mu: mailbox@30aa0000 {
	compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
	reg = <0x30aa0000 0x10000>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MN_CLK_MU_ROOT>;
	#mbox-cells = <2>;
};

Which seem to match the M7 part using 0x30ab0000.

there is the AN13340 @ https://www.nxp.com/webapp/sps/download/preDownload.jsp?render=true
And the code @ https://github.com/nxp-imx-support/cortex-M4_Cortex-A53_low_power_use_cases
(after the switch from codeaurora it is a bit hard to find the repos...)

But what I mean is from the AN13400 - 5.5.2 https://www.nxp.com/docs/en/application-note/AN13400.pdf

+static void imx_notify_m4_set_db(void)
+{
+ /* Use GIR[0] and enable interrupt */
+ mmio_setbits_32(IMX_MU_BASE + 0x24, BIT(19) | BIT(31));
+}
+
+static void imx_notify_m4_clear_db(void)
+{
+ /* Clear GIP[0] */
+ mmio_setbits_32(IMX_MU_BASE + 0x20, BIT(31));
+}
+
…
+ NOTICE("notify m4 by setting db! \n");
+ imx_notify_m4_set_db();
…
+ NOTICE("clear db! \n");
+ imx_notify_m4_clear_db();
…

I can't find code or patches about it.
Also IMX_MU_BASE seems to need to be additional defined to 0x30ab0000

The above is for the linux/atf part, like asked before for the M7 there should be an handler for the interrupt, too. 
So Is there an example available for it? All I see ist the wakeup Interrupt, which is already OK on my side.
What I need is the notification when A core goes to suspend.

[k_specka]

Hi @brian14 
This is still not solved.
As an alternative to use the mailbox driver - are the attachments of AN13400 available somewhere?
Like 0001-Switchenet-control-between-A-core-and-Mcore-for-cu.patch that is referenced in the AN. 

[k_specka]

@brian14 

I have done some testing but still having problems.

When the A53 is going to suspend sending the GIR via MU seems to be useful in ATF @ psci_main.c psci_system_suspend(...)
Kernel and drivers are down and ATF is going to power down.

When trying to send mmio_setbits_32(0x30ab0000 + 0x24, BIT(19) | BIT(31));
The suspend is aborted.

Do I need to set bit 31 for GIE on the M7 core before?
How is it done? Int0 for bit 31? like: MU_EnableInterrupts(MUB, kMU_GenInt0InterruptEnable ); 

Is there a way to add some data bits? 

Which interrupt will be triggered? Is there already a handler on mcuxpresso?
Do I need to register my own to the vector table?

Is example code available?

[k_specka]

I also checked some branches of imx-atf but IMX_MU_BASE is nowhere defined.
On MCUXpresso there is a #define MUB_BASE (0x30AB0000u)
So I expect #define IMX_MU_BASE U(0x30AB0000u) needs to be added to platform_def.h
Is this correct?

Is there an example available including patches and interrupt handler for M7?