IMX8 connect to Nand Flash

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

IMX8 connect to Nand Flash

677件の閲覧回数
shai_b
Senior Contributor II

Hello Team,

Ny customer has an inquiry about his new project:

My Nand Flash has 4 channels DQ0[0..7], DQ1[0..7], DQ2[0..7], DQ3[0..7],

What is the best way to connect it to the IMX8?

  • Each BUS will be connected to IMX through BUFFER when using GPIO from the IMX8 to control  which BUS is transfer ( .(option 1 in the attached file)
  • Connecting all the DATA and control signals together when using the CE[0..3]  from the IMX8 to control which BUS to transfer.(option 2 in the attached file)

 imx8nand_Slide1.PNG

 

option_1option_1

 

option_2option_2

 

Wating for your kind feedback, many thanks.

Regards,

Shai

ラベル(1)
タグ(1)
0 件の賞賛
3 返答(返信)

658件の閲覧回数
JosephAtNXP
NXP TechSupport
NXP TechSupport

Hi,

the recommendation would be to stick with the memory controller pins to achieve performance, using controlled-by-gpio buffers I think that would increase complexity and flexibility.

Thank you, regards

0 件の賞賛

641件の閲覧回数
shai_b
Senior Contributor II

@JosephAtNXP ,

The customer has stuck with the memory controller pins, please see their questions below:

  1. They need 2 GPIO that do not belong to memory control to control the buffer direction between the IMX8 and the Nand Flash.
  2. It is ok to short the all bus data together DQ0[0..7], DQ1[0..7], DQ2[0..7], DQ3[0..7],  and connect them to IMX8?

Waiting for your kind feedback, Thanks a lot.

Regards,

Shai

0 件の賞賛

563件の閲覧回数
JosephAtNXP
NXP TechSupport
NXP TechSupport

I think that the extra GPIOs would work but I haven't seen any performance over this action.

Shorting the 4-channel may not cause any problems as the different channels have their own control logic, right?

Why don't switch to a 8-bit NAND memory?

Thank you

0 件の賞賛