IMX6ULL: GPT2: INPUT CAPTURE 1: Failed to register an FALLING EDGE interrupt

[phaniteja]

Hello,

Here is my code snippet

platform_get_resource(pdev, IORESOURCE_MEM, 0);
devm_ioremap_resource(&pdev->dev, mem);
timer->irq = platform_get_irq(pdev, 0);
devm_request_irq(p_dev, timer->irq, r_irq_handler, 2, INPUT_PIN_DESC, pdev->dev.of_node);

DTS file:

gpttest: gpttest@020e8000 {
compatible = "fsl,imx-gpttest";
reg = <0x020e8000 0x4000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
<&clks IMX6UL_CLK_GPT2_SERIAL>;
clock-names = "ipg", "per";
};

My devm_request_irq call is failing here with the following out:

   genirq: Setting trigger mode 2 for irq 36 failed (irq_chip_set_type_parent+0x0/0x20)
   DRIVER_NAME: probe of 20e8000.gpt failed with error -22

I have done some debugging, from the function __irq_set_trigger() in manage.c while validating the chip->irq_set_type() its returning -22 (invald argument) error

Is there any chip level limitation for FALLING_EDGE interrupt for this particular gpt2 capture pin 1? Am I missing anything to register this?

Thanks,

Phani Movva

[gusarambula · Accepted solution]

Hello Phani Movva,

The capture trigger can be programmed to be a rising or/and falling edge. You would need to do this on the GPT Control Register GPTx_CR[IMn] bits. You can see more details of this register configuration on the i.MX6ULL Reference Manual. I would recommend to check the configuration of this register to see if that may be the problem.

I hope this helps!

Regards,