IAR workbench development ide and j-link ultra

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IAR workbench development ide and j-link ultra

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anilpathrut
Contributor I

Hello i am facing isssue while downloading application code on imx8mm6 i.e imx8m mini evk board

here using tool IAR workbench development IDE and J-link ultra debugger tool hardware

debug log details given below , please help on this

Mon Jul 05, 2021 10:24:42: IAR Embedded Workbench 9.10.2 (C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armPROC.dll)
Mon Jul 05, 2021 10:24:42: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\config\debugger\NXP\imx8m.dmac
Mon Jul 05, 2021 10:24:42: Logging to file: SW_Files\boards\evkmimx8mm\demo_apps\hello_world\iar\cspycomm.log
Mon Jul 05, 2021 10:24:42: JLINK command: ProjectFile = boards\evkmimx8mm\demo_apps\hello_world\iar\settings\hello_world_debug.jlink, return = 0
Mon Jul 05, 2021 10:24:42: Device "MIMX8MM6_M4" selected.
Mon Jul 05, 2021 10:24:42: DLL version: V7.20a, compiled May 7 2021 16:52:52
Mon Jul 05, 2021 10:24:42: Firmware: J-Link Ultra V4 compiled Apr 27 2021 16:36:54
Mon Jul 05, 2021 10:24:42: JTAG speed is initially set to: 32 kHz
Mon Jul 05, 2021 10:24:42: TotalIRLen = 4, IRPrint = 0x01
Mon Jul 05, 2021 10:24:42: JTAG chain detection found 1 devices:
Mon Jul 05, 2021 10:24:42: #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
Mon Jul 05, 2021 10:24:43: Failed to power up DAP
Mon Jul 05, 2021 10:24:43: TotalIRLen = 4, IRPrint = 0x01
Mon Jul 05, 2021 10:24:43: JTAG chain detection found 1 devices:
Mon Jul 05, 2021 10:24:43: #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
Mon Jul 05, 2021 10:24:43: DPv0 detected
Mon Jul 05, 2021 10:24:43: Scanning AP map to find all available APs
Mon Jul 05, 2021 10:24:43: AP[5]: Stopped AP scan as end of AP map has been reached
Mon Jul 05, 2021 10:24:43: AP[0]: AHB-AP (IDR: 0x64770001)
Mon Jul 05, 2021 10:24:43: AP[1]: APB-AP (IDR: 0x44770002)
Mon Jul 05, 2021 10:24:43: AP[2]: JTAG-AP (IDR: 0x24760010)
Mon Jul 05, 2021 10:24:43: AP[3]: JTAG-AP (IDR: 0x001C0030)
Mon Jul 05, 2021 10:24:43: AP[4]: AHB-AP (IDR: 0x24770011)
Mon Jul 05, 2021 10:24:43: Iterating through AP map to find AHB-AP to use
Mon Jul 05, 2021 10:24:43: AP[0]: Skipped. No ROM table (AHB-AP ROM base: 0x00000000)
Mon Jul 05, 2021 10:24:43: AP[1]: Skipped. Not an AHB-AP
Mon Jul 05, 2021 10:24:43: AP[2]: Skipped. Not an AHB-AP
Mon Jul 05, 2021 10:24:43: AP[3]: Skipped. Not an AHB-AP
Mon Jul 05, 2021 10:24:43: AP[4]: Core found
Mon Jul 05, 2021 10:24:43: AP[4]: AHB-AP ROM base: 0xE00FF000
Mon Jul 05, 2021 10:24:43: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Mon Jul 05, 2021 10:24:43: Found Cortex-M4 r0p1, Little endian.
Mon Jul 05, 2021 10:24:43: FPUnit: 6 code (BP) slots and 2 literal slots
Mon Jul 05, 2021 10:24:44: CoreSight components:
Mon Jul 05, 2021 10:24:44: ROMTbl[0] @ E00FF000
Mon Jul 05, 2021 10:24:44: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
Mon Jul 05, 2021 10:24:44: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
Mon Jul 05, 2021 10:24:44: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
Mon Jul 05, 2021 10:24:44: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
Mon Jul 05, 2021 10:24:44: ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM
Mon Jul 05, 2021 10:24:44: ROMTbl[0][7]: E0043000, CID: B105900D, PID: 001BB908 CSTF
Mon Jul 05, 2021 10:24:44: ROMTbl[0][8]: E0044000, CID: B105900D, PID: 004BB906 CTI
Mon Jul 05, 2021 10:24:44: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon Jul 05, 2021 10:24:44: Reset: Reset device via AIRCR.SYSRESETREQ.
Mon Jul 05, 2021 10:24:44: Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
Mon Jul 05, 2021 10:24:44: Reset: Using fallback: Reset pin.
Mon Jul 05, 2021 10:24:44: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon Jul 05, 2021 10:24:44: Reset: Reset device via reset pin
Mon Jul 05, 2021 10:24:44: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Mon Jul 05, 2021 10:24:44: Reset: Reconnecting and manually halting CPU.
Mon Jul 05, 2021 10:24:44: DPv0 detected
Mon Jul 05, 2021 10:24:44: AP map detection skipped. Manually configured AP map found.
Mon Jul 05, 2021 10:24:44: AP[0]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:44: AP[1]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:44: AP[2]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:44: AP[3]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:44: AP[4]: AHB-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:44: AP[4]: Core found
Mon Jul 05, 2021 10:24:44: AP[4]: AHB-AP ROM base: 0xE00FF000
Mon Jul 05, 2021 10:24:44: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Mon Jul 05, 2021 10:24:44: Found Cortex-M4 r0p1, Little endian.
Mon Jul 05, 2021 10:24:45: CPU could not be halted
Mon Jul 05, 2021 10:24:45: Reset: Core did not halt after reset, trying to disable WDT.
Mon Jul 05, 2021 10:24:45: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon Jul 05, 2021 10:24:45: Reset: Reset device via reset pin
Mon Jul 05, 2021 10:24:45: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Mon Jul 05, 2021 10:24:45: Reset: Reconnecting and manually halting CPU.
Mon Jul 05, 2021 10:24:45: DPv0 detected
Mon Jul 05, 2021 10:24:45: AP map detection skipped. Manually configured AP map found.
Mon Jul 05, 2021 10:24:45: AP[0]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:45: AP[1]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:45: AP[2]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:45: AP[3]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:45: AP[4]: AHB-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:45: AP[4]: Core found
Mon Jul 05, 2021 10:24:45: AP[4]: AHB-AP ROM base: 0xE00FF000
Mon Jul 05, 2021 10:24:45: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Mon Jul 05, 2021 10:24:45: Found Cortex-M4 r0p1, Little endian.
Mon Jul 05, 2021 10:24:45: CPU could not be halted
Mon Jul 05, 2021 10:24:45: CPU could not be halted
Mon Jul 05, 2021 10:24:45: Warning: Failed to halt CPU.
Mon Jul 05, 2021 10:24:45: Hardware reset with strategy 4 was performed
Mon Jul 05, 2021 10:24:45: Initial reset was performed
Mon Jul 05, 2021 10:24:45: Found 1 JTAG device, Total IRLen = 4:
Mon Jul 05, 2021 10:24:45: #0 Id: 0x5BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Mon Jul 05, 2021 10:24:45: CPU could not be halted
Mon Jul 05, 2021 10:24:49: Loaded debugee: SW_Files\boards\evkmimx8mm\demo_apps\hello_world\iar\debug\hello_world.bin
Mon Jul 05, 2021 10:24:49: Verification error at 0x1ffe'0002: mem = 0x00, file = 0x02
Mon Jul 05, 2021 10:24:49: Download completed but verification failed.
Mon Jul 05, 2021 10:24:49: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon Jul 05, 2021 10:24:49: Reset: Reset device via AIRCR.SYSRESETREQ.
Mon Jul 05, 2021 10:24:49: Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
Mon Jul 05, 2021 10:24:49: Reset: Using fallback: Reset pin.
Mon Jul 05, 2021 10:24:49: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon Jul 05, 2021 10:24:49: Reset: Reset device via reset pin
Mon Jul 05, 2021 10:24:50: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Mon Jul 05, 2021 10:24:50: Reset: Reconnecting and manually halting CPU.
Mon Jul 05, 2021 10:24:50: DPv0 detected
Mon Jul 05, 2021 10:24:50: AP map detection skipped. Manually configured AP map found.
Mon Jul 05, 2021 10:24:50: AP[0]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[1]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[2]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[3]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[4]: AHB-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[4]: Core found
Mon Jul 05, 2021 10:24:50: AP[4]: AHB-AP ROM base: 0xE00FF000
Mon Jul 05, 2021 10:24:50: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Mon Jul 05, 2021 10:24:50: Found Cortex-M4 r0p1, Little endian.
Mon Jul 05, 2021 10:24:50: CPU could not be halted
Mon Jul 05, 2021 10:24:50: Reset: Core did not halt after reset, trying to disable WDT.
Mon Jul 05, 2021 10:24:50: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon Jul 05, 2021 10:24:50: Reset: Reset device via reset pin
Mon Jul 05, 2021 10:24:50: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Mon Jul 05, 2021 10:24:50: Reset: Reconnecting and manually halting CPU.
Mon Jul 05, 2021 10:24:50: DPv0 detected
Mon Jul 05, 2021 10:24:50: AP map detection skipped. Manually configured AP map found.
Mon Jul 05, 2021 10:24:50: AP[0]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[1]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[2]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[3]: MEM-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[4]: AHB-AP (IDR: Not set)
Mon Jul 05, 2021 10:24:50: AP[4]: Core found
Mon Jul 05, 2021 10:24:50: AP[4]: AHB-AP ROM base: 0xE00FF000
Mon Jul 05, 2021 10:24:50: CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Mon Jul 05, 2021 10:24:50: Found Cortex-M4 r0p1, Little endian.
Mon Jul 05, 2021 10:24:50: CPU could not be halted
Mon Jul 05, 2021 10:24:50: CPU could not be halted
Mon Jul 05, 2021 10:24:50: Warning: Failed to halt CPU.
Mon Jul 05, 2021 10:24:50: Software reset was performed
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 17 (MSP) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 18 (PSP) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 20 (CFBP) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 15 (R15) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 0 (R0) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 1 (R1) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 2 (R2) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 3 (R3) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 4 (R4) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 5 (R5) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 6 (R6) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 7 (R7) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 8 (R8) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 9 (R9) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 10 (R10) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 11 (R11) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 12 (R12) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 17 (MSP) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 18 (PSP) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 14 (R14) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 15 (R15) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 16 (XPSR) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 20 (CFBP) while CPU is running
Mon Jul 05, 2021 10:24:50: Warning: Cannot read register 15 (R15) while CPU is running
Mon Jul 05, 2021 10:24:50: Target reset
Mon Jul 05, 2021 10:24:50: There were 1 error and 1 warning during the initialization of the debugging session.
Mon Jul 05, 2021 10:25:37: IAR Embedded Workbench 9.10.2 (C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armPROC.dll)
Mon Jul 05, 2021 10:25:38: Loading the jlink driver

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Anil

 

for debugging recommended to use  IAR tool patch for i.MX 8M Mini

and IAR revision/tools described in sect.3.1 Compiler/Debugger

Getting Started with MCUXpresso SDK for EVK-MIMX8MM.pdf,

sect.Chapter 3 Development tools MCUXpresso SDK Release Notes for EVK-MIMX8MM.pdf

documents included in M4 SDK_EVK-MIMX8MM available on

https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-i...

 

 

Best regards
igor

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anilpathrut
Contributor I

Thanks for the reply,

 

i have checked iar_support_patch_imx8mm , the process that i have used is "replaced the config folder in arm " i.e folder iar_support_patch_imx8mm->arm->config

and then tried to upload the hello_world demo application code on the imx8mm6 (imx8m mini evk board)

also tried with replacing whole arm folder from the "patch" to upload the demo application hello_world on to the imx8mm6(imx8mm mini evk board)

The Debugger tool which i am using for this , is j-link ultra+ version 4.4

but still facing same issue 

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anilpathrut
Contributor I

Waiting for the reply

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igorpadykov
NXP TechSupport
NXP TechSupport

below part of Getting Started with MCUXpresso SDK document :

 

1.jpg

Best regards
igor

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anilpathrut
Contributor I

Hello Sir,

 while installing IAR workbench development IDE already installed J-link driver, also externally installed diver  7.5.0 J-link. based on this we able to detect J-link, we checked in device manager showing the j-link port. also showing in diagnostic log ,check below

 

Mon Jul 05, 2021 10:24:42: JLINK command: ProjectFile = C:\Software\SW_Files\boards\evkmimx8mm\demo_apps\hello_world\iar\settings\hello_world_debug.jlink, return = 0
Mon Jul 05, 2021 10:24:42: Device "MIMX8MM6_M4" selected.
Mon Jul 05, 2021 10:24:42: DLL version: V7.20a, compiled May 7 2021 16:52:52
Mon Jul 05, 2021 10:24:42: Firmware: J-Link Ultra V4 compiled Apr 27 2021 16:36:54
Mon Jul 05, 2021 10:24:42: JTAG speed is initially set to: 32 kHz
Mon Jul 05, 2021 10:24:42: TotalIRLen = 4, IRPrint = 0x01
Mon Jul 05, 2021 10:24:42: JTAG chain detection found 1 devices:

but when we go for download application on target board imx8mm6 i.e imx8m mini evk board through IAR workbench development IDE.

we facing below issue

Mon Jul 05, 2021 10:24:45: CPU could not be halted
Mon Jul 05, 2021 10:24:49: Loaded debugee: C:\Software\SW_Files\boards\evkmimx8mm\demo_apps\hello_world\iar\debug\hello_world.bin
Mon Jul 05, 2021 10:24:49: Verification error at 0x1ffe'0002: mem = 0x00, file = 0x02
Mon Jul 05, 2021 10:24:49: Download completed but verification failed

above diagnostic log saying that CPU could not be halted ,verification error and Download completed but verification failed.

here we are using J-link ultra+  ,IAR worknech development IDE 9.10.2 , demo application code hello_wolrd from nxp provided SDK_2_9_1_EVK-MIMX8MM for the imx8m mini evk board

what is the reason for the CPU could not be halted  and verification failed

please confirm for J-link ultra supports to imx8m.

Waitting for the reply.

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anilpathrut
Contributor I

Waiting for your reply

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igorpadykov
NXP TechSupport
NXP TechSupport

as described in Getting Started with MCUXpresso SDK document  J-Link Ultra is not supported,

suggested to try with J-Link Plus.

 

Best regards
igor

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