I.MX6DL, 2 GByte LPDDR2 problem

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I.MX6DL, 2 GByte LPDDR2 problem

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cseven
Contributor I

Hi, In our design we are using Micron EDBA232B2PB , 2 GByte LPDDR2 memory with I.MX6DL processor. The problem is that proccessor  can not recognize 2 GByte memory and it behaves like just 1 GByte memory connected to MMDC. In other words , we can use just 1 GByte memory space of 2 Gbyte. Our register programming script is attached.I can not find why the processor memory controller can not find remaining 1 Gbyte memory.Can you help us to solve this problem

 

Regards,

Cüneyt Seven

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3 Replies

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igorpadykov
NXP Employee
NXP Employee

Hi Cüney

 

one can try rev.1.3 RPA tool from

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX6DL-LPDDR2-Register-Programming-Aid/...

and try to set MMDCx_MDMISC register, LPDDR2_2CH Field to '0' as described on

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6Solo-LPDDR2-Registry-Settings/ta-p...

 

Best regards
igor

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cseven
Contributor I

Hi Igor,

Thank you for quick response. I have just used RPA v1.3.  As you recommend, I modified my script by setting   MMDCx_MDMISC register, LPDDR2_2CH Field to '0'.  On my board one single channel LPDDR2 is connected to MMDC0. But there is still problem. After changing  script , DDR stress tool test is also failed. Maybe, there is a bug for one channel test when lpddr2 device is connected to ch0. 

The confusing point is that , in the reference manual  for 1-channel LPDDR2 mode it says "MMDCx _MDASP[CS0_END]  address begins at 0x10000000" for both channel ??? However, in the RPA script number of channel usage does not affect  CH0  base address and CH0  CS0_end.  CH_0 base address always starts from 0x8000000, CH1 base address starts from 0x10000000  whether we are using or not two channel.  In  my case , as I connect lpddr2  to CH0,    CS0_END is at 0xc0000000 address in the script due to  2 GByte space. Also its base address is at  0x80000000.Reference manual explanation conflicts with RPA script setting.

IN THE REFERNCE MANUAL:

In DDR3 and 1-channel LPDDR2 mode: 

MMDCx _MDASP[CS0_END] should be set to DDR_CS_SIZE/32MB + 0x7 (DDR base address begins at 0x10000000)

 

In 2-channel LPDDR2 mode:

MMDC0_MDASP[CS0_END] should be set to DDR_CS_SIZE/32M + 0x3f (channel 0 base address begins at 0x80000000)

MMDC1_MDASP[CS0_END] should be set to DDR_CS_SIZE/32M + 0x7 (channel 1 base address begins at 0x10000000);

Best regards,

Cüneyt

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igorpadykov
NXP Employee
NXP Employee

Hi Cüneyt

 

I asked internally and was adviced that issue may be related to ERR010481 

Chip Errata for the i.MX 6Solo/6DualLite

MMDC register programming setting looks fine.

 

Best regards
igor

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