How to shorten the gap between ecspi byte transfer

[stevenyu]

Hi all,

We use ecspi to transfer data traffic, however, the throughput is only 3.5Mbps RX, 4.2Mbps TX. It looks like the RX path has some problem, so we use oscilloscope to check and found the gap between SPI byte transfer is a little big (~361) compared to other CPU (Raspberry3 : ~94). Do you know how to configure the gap between each byte transfer?

The SPI speed is configured to 19000000, and each byte transfer in proper speed, only the gap is a little big. 

Thanks.

Regards,

Steven Yu

[igorpadykov]

Hi Steven

there is SAMPLE_PERIOD in ECSPIx_PERIODREG register for

inserting wait states of data transfers. Except it there is no way to control

 throughput or shorten gaps, as gaps are introduced by processor internal buses delays.

One can try to decrease buses loading by removing some graphic applications or

decreasing lcds frame rate.

Best regards
igor
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[stevenyu]

Hi Igor and All,

We found the SAMPLE_PERIOD is 0 by default. If we configure to 0x0, 0x2, 0x100, we found the gap become bigger and bigger. However, the smallest gap is 357~361ns.

We also try to change spi speed from 16M to 8M, and found the gap will become bigger according to spi speed. Therefore, the gap does refer to spi speed. Do you have any other idea why the gap will refer the spi speed ? 

Regards,

Steven YU

[igorpadykov]

Hi Steven

one can try approach as with gpios:

https://community.nxp.com/message/465097?commentID=465097#comment-465097 

Best regards
igor