How to generate MSI interrupt on i.MX6 in PCIe EP/endpoint mode

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How to generate MSI interrupt on i.MX6 in PCIe EP/endpoint mode

Contributor III




I am sharing the information that should be documented in the RM but was not and it was very annoying to get thru the issues to use i.MX6 in EP mode. We managed to use the chip to support inbound transactions, outbound transactions and MSI generation.



To generate MSI from i.MX6 in EP mode to the RC you need to do:

1) let the Linux on RC enumerate all PCIe endpoints

2) on RC Linux load the driver for EP that initializes all required interrupt settings for RC and EP




     .... and all the usuall PCI stuff. Attached example of very ugly driver we used to test the MSI.

3) manually modify settings on RC:

     cd /unit_tests/

     ./memtool -32 0x1ffc828=0xFFFFFFFF

     ./memtool -32 0x1ffc82c=0x0


  This unmasks all MSI interrupt vectors. It is not nice, but you can check which one should really be unmasked. It looks Linux by default enables wrong vectors.

4) on the EP issue interrupt by writing 1 to the address assigned by RC for the MSI (you can get this address in 0x1FFC054

     ./memtool 0x1ff8000=1



This generates MSI to RC:


5) check interrupt counters on RC

     cat /proc/interrupts | grep MSI

     497:          2          0          0          0  PCIe-MSI




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