Generally section 33.2.9 “ITU-R BT.656 Digital Video Interface (DVI)”
of the i.MX28 Reference Manual provides information about BT.656 using :
“ITU-R BT.656 Digital Video Interface shown below transmits 4:2:2 YCbCr digital
component video to a digital video encoder that can translate it into 525/60 or 625/50
analog TV signal. Unique timing codes (timing reference signals) are embedded within
the video stream to indicate the different timing events that would have been otherwise
indicated by VSYNC, HSYNC and BLANK signals. The hardware supports 8-bit data
transfers; the pins are shared with the lower 8 bits of LCD data bus. The LCD_RS pin is
shared with the clock signal of the interface (called CCIRCLK here for uniqueness).
CCIRCLK also can be obtained on the LCD_DOTCK pin. The mode shares the write
FIFO with the LCD interface and the associated pipeline. The programmable parameters
in registers HW_LCDIF_DVICTRL0-3 allow setting the total number of horizontal lines
per frame, vertical and horizontal blanking interval, odd and even field start and end
positions, and so on. In short, these parameters are provided to ensure that the hardware
has enough flexibility to generate the right 525/60 or 625/50 data streams. Most of the
initialization steps in Initializing the LCDIF such as data shifting, swizzle, and so on, are
applicable to DVI mode also. The register descriptions in the programmable registers
section at the end of this chapter include example code for programming the
DVICTRL0-3 registers.
In DVI mode, HW_LCDIF_CTRL_BYPASS_COUNT bit must be set to 1. To end the
current transfer, the software should make the DVI_MODE bit the value 0, so that all
data that is currently in the LCDIF LFIFO and TXFIFO is transmitted. Once that transfer
is complete, the block will automatically clear the RUN bit and assert the
cur_frame_done interrupt.”
So, please take a look at the examples in following sections of the i.MX28 Reference Manual :
- 33.4.13 “Digital Video Interface Control0 Register (HW_LCDIF_DVICTRL0)”
- 33.4.14 “Digital Video Interface Control1 Register (HW_LCDIF_DVICTRL1)”
- 33.4.15 “Digital Video Interface Control2 Register (HW_LCDIF_DVICTRL2)”
- 33.4.16 “Digital Video Interface Control3 Register (HW_LCDIF_DVICTRL3)”
- 33.4.17 “Digital Video Interface Control4 Register (HW_LCDIF_DVICTRL4)”
For general LCDIF initialization please refer to the OBDS package
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