How do I modify the max payload size for PCIe on the i.MX8

[GregT]

Hi,

I'm trying to increase it to 1024.  The reference manual says that it supports up to 4096.  I've tried patching the pci-imx6.c file with the code snippet below but it always hangs on boot up.  Here is the register offset and masking.  We need to set the max payload size before enumeration because the fpga end point needs the payload size to be 1024.

At the top of the pci-imx6.c file I put this.

/* PCIe Root Complex registers (memory-mapped) */
#define PCIE_RC_DEVICE_CAPABILITIES_REG 0x74
#define PCIE_RC_DCR_MAXPAYLOAD_MASK 0x7
#define PCIE_RC_DCR_MAXPAYLOAD_1024 0x3
#define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS 0x78
#define PCIE_RC_DCDS_MAXPAYLOAD_MASK 0xe0
#define PCIE_RC_DCDS_MAXPAYLOAD_1024 0x60

And I put the code below at the end of the imx6_pcie_probe function.

// change the max payload
tmp = dw_pcie_readl_rc(pp, PCIE_RC_DEVICE_CAPABILITIES_REG);
tmp &= ~PCIE_RC_DCR_MAXPAYLOAD_MASK;
tmp |= PCIE_RC_DCR_MAXPAYLOAD_1024;
dev_info(dev, "Change the max payload size, dev cap reg 0x%08x.", tmp);
dw_pcie_writel_rc(pp, PCIE_RC_DEVICE_CAPABILITIES_REG, tmp);
tmp = dw_pcie_readl_rc(pp, PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS);
tmp &= ~PCIE_RC_DCDS_MAXPAYLOAD_MASK;
tmp |= PCIE_RC_DCDS_MAXPAYLOAD_1024;
dev_info(dev, "Change the max payload size, dev ctrl status reg 0x%08x.", tmp);
dw_pcie_writel_rc(pp, PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS, tmp);

Thanks,

Greg

[GregT]

After further investigation even though the config space has a larger TLP (1024 bytes) the FPGA team indicates the processor locks up when we try to DMA a packet larger than 128 bytes.  Will do further investigation.

[abelal]

Hi @GregT, were you able to resolve the problem of processor locking up with DMA packets larger than 128 bytes? If yes, can you please share the investigation results?

[GregT]

Our SOM provider Compulabs stated the i.MX8 processor TLP size is limited to 128 bytes. If we increase the size over 128 but still only use max of 128 bytes the performance with our Wifi chip that uses PCIe suffered.  So we left the max TLP size at 128.  NXP needs to increase the max TLP size in their i.MX8 processor to support larger TLPs.

[GregT]

I tried adding a pci quirk which gets executed but does not change the max payload size.

/* Set the max payload size for the imx8 root complex to be 1024
*/
static void fixup_mpss_1024(struct pci_dev *dev)
{
    dev->pcie_mpss = 3; /* 1024 bytes */
    printk(KERN_INFO "Set i.MX8 root complex (0xabcd16c3) max payload size to 1024.\n");
}
DECLARE_PCI_FIXUP_HEADER(0x16c3, 0xabcd, fixup_mpss_1024);

I do see the printk output in the kernel log.

user.info kernel: [ 2.023110] Set i.MX8 root complex (0xabcd16c3) max payload size to 1024.

[GregT]

Finally got it to work by read/modify/writing the pci config registers inside the quirk.

/* Set the max payload size for the imx8 root complex to be 1024
*/
static void fixup_mpss_1024(struct pci_dev *dev)
{
    u32 config;

    pci_read_config_dword(dev, 0x74, &config);
    config &= 0xfffffffc;
    config |= 0x3;
    pci_write_config_dword(dev, 0x74, config);
    pci_read_config_dword(dev, 0x78, &config);
    config &= 0xffffcf9f;
    config |= 0x3060;
    pci_write_config_dword(dev, 0x78, config);
    printk(KERN_INFO "Set i.MX8 root complex (0xabcd16c3) max payload size and max read request to 1024.\n");
}
DECLARE_PCI_FIXUP_HEADER(0x16c3, 0xabcd, fixup_mpss_1024);