Hello,
We have a custom board based on the imx8mn-ddr3l-evk SOM, except it uses DDR4 instead of DDR3L. We have been able to create a custom BSP (modify uboot & imxboot) and successfully boot Linux based on past imx BSPs, with the latest version being on LF5.15.71_2.2.0 (uboot v2022.04). However, we just attempted to update our BSP to LF6.1.55_2.2.0 (uboot v2023.04), and we are getting the error below when trying to load the generated yocto image using UUU. The full output is attached.

We believe the SPL is not loading, and we don't think it is a DDR init issue. We do not get any output on the UART console, and the PMIC rails voltages are not being configured, which is one of the SPL functions that is called before the DDR init function. We put multiple console messages at different stages within spl.c and are getting nothing. We know the board is okay cause we are able to boot our latest image compiled based on LF5.15.71_2.2.0.
The board files (<machine>.conf, <machine>_defconf, <machine>.dts, spl.c, etc.) in this BSP are very similar to the old working BSP with few changes introduced to match updates introduced to imx8mn_evk board files. We tried multiple configurations and still got nothing out. We basically have the following questions:
- Are all machines included in the imx yocto release (ex: imx8mn_evk.conf, imx8mn_ddr3l_evk.conf, and imx8mn_ddr4_evk.conf) have been tested to boot Linux?
- Can a JTAG connection with a JLink Flash debugger offer us more useful information? Is there any documentation to follow? I see some for other debuggers (e.g., ARM DSTREAM), but I'm not sure if we can use segger JLink.
- How can we access BOOT ROM Log Events? AN12853 discusses the available info, but we're not sure how to access it if SPL is not loading. We thought JTAG, but imx8mnrm states that JTAG is not accessible during the initial ROM boot.
- Any ideas on how to troubleshoot this issue and move forward? We are running out of ideas.
Thank you.