Dear Team,
We are designing a custom board based on IMX8M Plus Processor. We have the following listed queries to get clarified with. Kindly do the same.
1) Updates from A0 to A1 Silicon CPU- Ball B11 : USB1_ID & Ball E12 : USB2_ID (OTG ID pins from carrier card was connected in A0 CPU) now got changed to Ball B11 : USB1_DNU & Ball E12 : USB2_DNU (which is Do not use as per NXP) -so to which pin we can connect USB OTG ID signal for both USB controllers? What other design consideration we have to take care, Please clarify?
2)In "Table 75. Interface allocation during boot" Section of Datasheet USDHC1 boot Option is there . But in Reference Manual in "Table 6-1. Boot MODE pin settings" USDHC1 boot option is shown. Is Boot option available for uSDHC1 controller ?if yes what must be the Boot MODE pin settings for the same?
3)Kindly provide the details changes list between A0 & A1 Silicon CPU in terms of Hardware & Software design.
4)For LPDDR4 routing its recommended to do delay matching in time (in ps. Is it OK to do delay matching in length (mils),,if ok can we convert package delay provided in ps to mils (1ps=6mils) ?
5)Is 2GB LPDDR4 memory is sufficient to develop Linux and Android BSP. Kindly share Software memory map of the Processor.
6)We would like to know details on multiple display supported in iMX8M Plus. Please share display selection guide for iMX8M Plus. We want to know what is the maximum resolution will be supported in each display (MIPI DSI,HDMI,LVDS) when multiple display is supported.
7)HDMI TX Controller details in Reference Manual are not there. Please provide updated Reference Manual with the details
Regards,
Shruthi
Hi Shruthi
this part is "PRE-PRODUCTION" part as described on below i.MX8M Plus product page
So it is not officially supported yet. Full support, including full documentation will be provided after
official product launch. Before that date all support can be provided through local marketing channel.
Best regards
igor