GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

[Chengting]

We'd plan to use GPIO4 for data transfer(i.MX8P dual core) . Thus we gave a test of the GPIO speed.

M7 part test.

//skipping the iomux setting and pin setting

while (i<100 000 000)

{

     //read

     GPIO_PinRead(GPIO4,0);

     //pulling high
     GPIO_PinWrite(GPIO4,18,1);
 
     //pulling low
     GPIO_PinWrite(GPIO4,18,0);
      i++;
}

It cost 33 s, totally, the speed is far behind the IPG_clk we set, 133Mhz.

As the image show, every high last 65 ns, every repeat last 330 ns.

If the read cost 2 clock loop, the clock time is 30 ns, which is 33Mhz, far behind the 133 hHz in reference Manual.

[Chengting]

Thanks for your reply. How do I know the correct speed (or the highest speed the platform can support)?

That's what I really really need. Thank you again.

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
{
    assert(pin < 32U);

    return (((base->DR) >> pin) & 0x1U);
}

void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
{
    assert(pin < 32U);
    if (output == 0U)
    {
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR)
        base->DR_CLEAR = (1UL << pin);
#else
        base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ //==> this branch
#endif
    }
    else
    {
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET)
        base->DR_SET = (1UL << pin);
#else
        base->DR |= (1UL << pin);  /* Set pin output to high level.*/  //==> this branch
#endif
    }
}

[Sanket_Parekh]

Hi @Chengting ,

I hope you are doing well.

The correct gpio togging speed is not documented anywhere as it depends upon many things and overheads of applications can also affect it.

Thanks & Regards,

Sanket Parekh

[Sanket_Parekh]

Hi @Chengting 

I hope you are doing well.

The clock source for gpio modules is ipg_clk_s (Clock root: IPG_CLK_ROOT).

Here, ipg_clk_s is used for synchronization in gpio sampling, reading register values, etc...

It does not mean the frequency at which gpio output toggles in this example.

This test does have the overhead of other instructions (loop condition, increment,).

GPIO_PinWrite() function also contains various conditional branching.

Thanks & Regards

Sanket Parekh

[Chengting]

Thanks for your reply. How do I know the correct speed (or the highest speed the platform can support)?

That's what I really really need. Thank you again.

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
{
    assert(pin < 32U);

    return (((base->DR) >> pin) & 0x1U);
}

void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
{
    assert(pin < 32U);
    if (output == 0U)
    {
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR)
        base->DR_CLEAR = (1UL << pin);
#else
        base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ //==> this branch
#endif
    }
    else
    {
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET)
        base->DR_SET = (1UL << pin);
#else
        base->DR |= (1UL << pin);  /* Set pin output to high level.*/  //==> this branch
#endif
    }
}