For i.MX8-QXP-C0-mek, is it possible to read the PPS output from ENET0_REFCLK_125M_25M?

[killedByBugs]

Hi,

I would like to read the PPS output of i.MX8-QXP-C0-mek on my oscilliscope.

I have found "i.MX8 serials IEEE1588 1pps test procedure" page which introduces how to get the 1pps output of i.MX8MP board. 

For i.MX8-QXP, I found ENET0_REFCLK_125M_25M pin of the board might be able to output the PPS signal. (related document: IMX8DQXP_reference_manual) 

I checked the pin on the schematic diagram of the board, the pin ENET0_REFCLK_125M_25M is on "i.MX8QXP-ENET(U12G)" (as the following diagram.) I couldn't find any test point connected to this pin. Also, U12G should be the IMX8 CPU (maybe it is under the fan of the board). It is hard to probe its pins.

Then, I found the pin is connected to "USB_TYPEC_SEL" which is also connected to "U37". (as the following diagram) 

I plan to read this pin to the oscilloscope. However, I find the pins are too tiny to probe:

Is it any other way to get the PPS output from the pin ENET0_REFCLK_125M_25M?

Thank you in advance.

Kind Regards,

Jim

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

There is no way,

FYI U12G is a segmented schematic part of the processor (as guessed, it's under the heatsink) but the ball pitch would be more problematic,

As seen, the signal is a selector for a switch so, if you're going to test pps disable USB C functionality,

Finally, the signal is just that trace without testpoints, so you should probe the switch pin or go for a custom board design, due to there are no other pins iomuxed for this.

Regards

[killedByBugs]

Hi, 

I have tried your suggestion. However, I still couldn't get any square wave from the pin  "ENET0_REFCLK_125M_25M". Probably, I have done something wrong. Can you please have a look on my steps of operations? Please let me know what steps I have taken wrong:

1. Editing device tree related file in the work-shared dir:

on /arch/arm64/boot/dts/freescale/imx8x-mek.dtsi (the imx8qxp-mek.dts file includes this file):

@@ -1396,6 +1396,8 @@
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
+ // added:
+ IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS 0x06400040

2. removing the conflicted one (USB TYPEC):

@@ -1547,7 +1549,8 @@

pinctrl_typec_mux: typecmuxgrp {
fsl,pins = <
- IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
+ /* ----- to avoid conflicts, remove the following line ---------- */
+ //IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60

3. After adding those patches I wrote, "bitbake" again and burned the image to the board.

4.1. In Linux system: run ptp4l:

ptp4l -l 6 -m -i eth0 -p /dev/ptp0 &

4.2. enable PPS:

echo 1 > /sys/class/ptp/ptp0/pps_enable

4.3.  change the duty cycle of the PPS clock for a close to 50% ratio

echo "0 0 0 1 1" > /sys/class/ptp/ptp0/period 

5. probe pin USB_TYPEC_SEL pin (pin 12) of U37

Kind Regards,

Jim

[JosephAtNXP]

Hi,

Could you try running ptp4l like this:

Transport on UDP IPV4 with E2E delay mechanism: ptp4l -A -4 -H -m -i eth0

Regards

[killedByBugs]

Hi Joseph,

Previously, I always use PTP4L command before testing. It doesn't work.

Can you have a look on the 2 steps I have done? Does it look correct?:

1. Editing device tree related file in the work-shared dir:

on /arch/arm64/boot/dts/freescale/imx8x-mek.dtsi (the imx8qxp-mek.dts file includes this file):

@@ -1396,6 +1396,8 @@
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
+ // added:
+ IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS 0x06400040

2. removing the conflicted one (USB TYPEC):

@@ -1547,7 +1549,8 @@

pinctrl_typec_mux: typecmuxgrp {
fsl,pins = <
- IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
+ /* ----- to avoid conflicts, remove the following line ---------- */
+ //IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60

Regards,