FlexSPI RFDR buffer value query for various clock frequency

[kirans]

I am trying to configure the maximum Clock frequency allowed for the FlexSPI operation in quad mode for external flash read operation and I am recieving the value 0xC1 in RFDR[0] at API "FLEXSPI_TransferBlocking" and it is not coming out of the bus busy state and failing. 

I tried to configure the clock frequency to 400MHz and used the divider 2 to achieve 200M value just out of curiosity. 

I would like to know what does this value at RFDR indicate and who is responsible to update?

If I use the divider value 3, the operation is successfull with RFDR[0] value as 0x80 and so on changes for various loop sequences.

[Omar_Anguiano · Accepted solution]

Hello
I hope you are well.

RFDR registers provide read access to IP RX FIFO by IPS bus. The read value is unknown for read access to invalid entries in IP RX FIFO.
It is important that the FlexSPI memory has a limitation on its clock speed and it is around 133-166Mhz depending on the specific device you are using.

Best regards,
Omar

[kirans]

Thanks Omar for the valuable inputs. I guess it has answered my question. If i get any doubts will post it here.

Thanks again