FlexSPI Parallel Flash Mode for 2 MT25QL flashes

[GopiKrishna]

Hi,

We have connected two same MT25QL flash devices one on port A1 and port B1, we are trying to enable the parallel flash mode in FlexSPI module, we have set the fallowing settings in corresponding registers.

In AHB mode for read operation

ahbcr -> APAREN to 1  ,In this mode we have observed parallel flash mode seems to be enabled.  

In IP command mode for write and read operation we are setting 

ipcr1 -> IPAREN to 1 and setting the IPCMD trigger, In this configuration we have observed that even though parallel mode setting is enabled it is still operating in the Individual mode (both write and read).

as we want to use the IP command mode could you please confirm whether we are missing any other settings? or could you please list what are the registers in sequence we need to configure to enable parallel flash mode in FlexSPI in IMX8QM5xxx?

[Sanket_Parekh]

Hi @GopiKrishna 

I hope you are doing well

How you are setting the register bit IPCR1[IPAREN]?

Kindly confirm that the register value is changed successfully by reading it from the kernel using the devmem2 tool or memtool.

For more details regarding the IP Command, kindly refer to section 19.3.4.9 Flash access by IP Command from the reference manual IMX8QMRM.

Thanks & Regards

Sanket Parekh

[GopiKrishna]

Hi Sanket,

Greetings 

I have configured my code as per section 19.3.4.9 Flash access by IP Command, I am setting the IPCR0 with flash address, IPCR1 register with IPARREN bit to 1, SEQID, and num of bytes, after that, I am triggering IPCMD register with 0x1.

for AHB read mode I am setting APAREN bit in AHBCR register but I am seeing the AHB mode is also not stable, sometimes I am seeing all data as 0xffffffff, or alternate 0xff(ex: like  0xff 0x2 0xff 0x3 data is 0x1 0x2 0x3 0x4)

I would like to confirm if is there any other register setting that I am missing. or when I should exactly set that IPAREN bit in IPCR1 and APAREN bit in AHBCR

is there any example code in which parallel flash mode is enabled and used? That would be more helpful if one such is there in SDK

[Sanket_Parekh]

Hi @GopiKrishna 

I hope you are doing well

According to the reference manual of IMX8QM, the register settings are as below.

"Individual mode and parallel mode is determined statically by register field IPCR1[IPAREN] (for IP command) or AHBCR[APAREN] (for AHB command)."

is there any example code in which parallel flash mode is enabled and used?

=> Yes, One can refer to the MCUXpresso SDK Builder tool to download the SDK for a particular processor.

The example code can be referred to from the file "devices/MIMX8QM6/drivers/fsl_flexspi.h" in the SDK.

The description of the APIs of that SDK code can be referred to from the below link.

i.e void FLEXSPI_EnableIPParallelMode() and void FLEXSPI_EnableAHBParallelMode();

https://mcuxpresso.nxp.com/api_doc/dev/721/group__flexspi.html

https://mcuxpresso.nxp.com/api_doc/dev/1581/group__flexspi.html

Thanks & Regards

Sanket Parekh

[GopiKrishna]

Hi @Sanket_Parekh 

Thank you so much for your reply It was pretty helpful. While implementing Parallel Flash Mode, we observed a few things as mentioned below:

1. As per the reference manual, we have to send the flash address divided by two for erase, program, and read operations to perform in parallel mode. PFB reference manual snapshot.

But, we observed the FSPI is not working as expected as per the below highlighted note. Instead, it was working fine when passing the address without dividing by two which seems the module itself taking care of the address division. Can you confirm the address to be passed in parallel mode?

2. We are enabling 4 Byte addressing mode during initialization and reading the Flag Status Register from the flash chips in parallel mode and observed the 4-Byte addressing bit is not getting set, whereas in the individual mode, it is set as expected. Can you please provide your input on this behavior when FSPI is reading flag status in parallel mode?

Request you to please provide your input.

[Sanket_Parekh]

Hi @GopiKrishna,

I hope you are doing well

Please find the answer below.

1) Yes, The module itself manages the addressing according to the individual or parallel mode of Flexspi.

2)Kindly share the steps of how you are trying to enable 4 Byte addressing mode and how you are reading the Flag Status Register to further debug the issue.

Thanks & Regards,

Sanket Parekh

[GopiKrishna]

Hi @Sanket_Parekh ,

  Thank you for your response and confirmation. for point 1 It would be good if the module itself is doing the division.

and for point number 2, Below are the steps for the observation in parallel mode:

1. Initialize the FSPI in parallel mode and populate the LUT.
2. Trigger IP-based command (parallel mode) to enable 4-byte address mode(as it will send the same command to both flashes).
3. Trigger IP-based command (parallel mode) to read the flag status register to verify the addressing bit is set for both flash chips in the receive FIFO. PFB snapshot for register bit.

The same steps are repeated by initializing in the individual mode and observed the addressing bit is set on the flash device. But, In parallel mode we observed the bit is not set on both flash chips. Hope, it will helps you to investigate further.

[Sanket_Parekh]

HI @GopiKrishna 

I hope you are doing well

Kindly share the command which you are implementing to enable the 4-byte address mode.

Thanks & Regards,
Sanket Parekh

[GopiKrishna]

Hi @Sanket_Parekh 

Greetings!

Sorry, I was unable to respond as the NXP portal is under maintenance. We are using the 0xB7 command for enabling the 4-Byte address mode and sending it to both the flash devices by enabling parallel mode

[Sanket_Parekh]

Hello @GopiKrishna,

I hope you are doing well

The command is correct for setting 4-byte addressing.
For the bits you are reading, it is mentioned that "All bits are volatile and are reset to zero on power-up." Please check bit 0 from Table 7: Nonvolatile Configuration Register from the datasheet to confirm the number of address bytes for a command.

further, confirm if you were able to perform the operation with 4-byte addressing mode with success or not.
i.e
1)READ MEMORY Operations with 4-Byte Address.
2)ERASE Operations with 4-Byte Address etc.

Thanks & Regards,
Sanket Parekh