Hello Champs,
In the Errata ERR005852 "Analog: Transition from Deep Sleep Mode to LDO Bypass Mode may
cause the slow response of the VDDARM_CAP output".
The workaround is "The software workaround to prevent this issue it to switch to analog bypass mode (0x1E), prior to
entering DSM, and then, revert to the normal bypass mode, when exiting from DSM"
Does this mean that 11110(0x1E) is a special value which turns digital LDO into "analog bypass mode"?
Best regards,
Nori Shinozaki
已解决! 转到解答。
Hi Nori
LDO "analog bypass mode" IMX6DQRM
sect.50.7.4 Digital Regulator Core Register (PMU_REG_CORE)
is value:
11111 Power FET switched full on. No regulation.
so description in errata can be considered as misprint.
Best regards
igor
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