Hello,
i want to use the EIM-Interface for comunication between an IMX6Q and an FPGA for data transmission. I am using it in 16bit multiplexed A/D synchronous mode, using CLK, CS1, LBA, OE, RW, 0..15 of Data and want to read / write 32bit within one access. I am using the following register configuration:
CSnGCR1 0x19120BF
CSnGCR2 0x0
CSnRCR1 0x2020000
CSnRCR2 0x0
CSnWCR1 0x2080000
CSnWCR2 0x0
WCR 0x120
WIAR 0x10
The BCLK is running on 44MHz and i was able to start a read- and write-access successful.
But i found a strange behavoir of the EIM_Clk/BCLK. If the EIM is in idle, so chip select is high, the clock level is randomly on an high or low level. That means when an access begins (CS goes on low), the clock starts with a falling edge , when the idle-level of the clk is high, or with a rising edge, when the idle-level of the clk was low before. After the end of an access the clk goes back to its last level (so when high before, its high and if low before the access its low again). That means as long as the device is turned on, the idle-level is always the same and it only changes, if i restart the device. I made an abstract picture for a read-access:
I dont know if this is maybe a problem of our device in hardware, so i want to ask first, if there is any setting in the registers / kernel / driver that can effect this behavoir.
Hello,
According to i.MX6 Datasheet: "All EIM output control signals may be asserted and deasserted by an internal
clock synchronized to the EIM_BCLK rising edge according to corresponding assertion/negation control fields."
So, only active rising edge is guaranteed.
Have a great day,
Yuri
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Hello Yuri,
thank your, for your answer. Sadly it doesnt help me much with the problem. Why is the clock-level randomy high or low after the restart/boot of the device, when the EIM is in idle? As the datasheet says, i expect a low level in idle so that there will be always a rising edge, if the EIM access starts and the clock begins to run. Is it possible to affect the clock-level-state in idle with some settings (setup of registers or within the devicetree or something else)?
Hello,
The EIM will assert correct address and data on rising clock edge.
Data are sampled on rising edge too.
So, custom design should be oriented for such operations.
Regards,
Yuri.