Hello,
My team and I are seeking a bit of clarification on implementing DDR4 memory as the external memory for i.MX8M Nano UltraLite Solo (MIMX8MN1CVPIZAA). This uses the 11x11mm package. However, when looking at the design guide (IMX8MNHDG.pdf), we can see from Table 21 that the DDR4 function pin PARITY (aka CA Parity or Par) cannot be assigned to the DRAM_AC27 ball as it isn't present on the 11x11mm package. I've attached the table for reference.
For context: myself and my team are designing a SOM, which is based on the i.MX 8M Nano DDR4 EVK board and follows the hardware user guide (IMX8MNEVKHUG).
Our DDR4 external memory part number is MT40A1G16RC-062E, which according to this post is a validated memory.
I'm pretty sure that the Parity pin can be left unused (floating) in DDR4 so the IMX8M nano ultralite solo should still support DDR4.
1) Is this correct, that we can use DDR4 with this processor? If not this means that IMX8M Nano UL Solo may not support DDR4 which seems to contrast with the fact sheet and we'll need to switch to LPDDR4 or DDR3.
2) Is NXP aware of any other changes that may be required for DDR4 to work with the 11x11mm package?
For example, do we need to make edits to the ddr_init functions in u-boot to disable C/A Parity checks in the DDR4 memory?
Thanks for reading this!
