Hi community,
Our partner have a question about i.MX6DQ.
They want to know how much the current is output from VDD_CACHE_CAP.
We understood it should be shorted to VDDSOC_CAP, but didn't understand how bold line is needed between VDD_CACHE_CAP and VDDSOC_CAP about board layout since there is no current information.
Best Regards,
Satoshi Shimoda
解決済! 解決策の投稿を見る。
My apologies, Satoshi Shimoda,
I investigated but we do not have information of the current output from VDDSOC_CAP. VDD_CACHE_CAP is an input for the cache supply and is feed from VDDSOC_CAP.
One alternative is looking at the i.MX6 SABRE and use the same line width, which I would recommend.
Another option would be using the LDO maximum supply current in order to have a maximum value of the SOC supply current in order to determine how much VDDSOC_CAP can provide. According to Table 8 of the i.MX6Q Datasheet that would be around 2A and take that as an maximum in order to be safe.
Would you reply to this question?
Deadline for layout design is imminent, so I would appreciate it if you could give me a advice.
Best Regards,
Satoshi Shimoda
The i.MX6 VDDSOC_CAP output current is not specified. We can estimate this current of 1-2A during power up. Use this estimation for trace widths and via sizes.
Have a great day,
Pavel
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My apologies, Satoshi Shimoda,
I investigated but we do not have information of the current output from VDDSOC_CAP. VDD_CACHE_CAP is an input for the cache supply and is feed from VDDSOC_CAP.
One alternative is looking at the i.MX6 SABRE and use the same line width, which I would recommend.
Another option would be using the LDO maximum supply current in order to have a maximum value of the SOC supply current in order to determine how much VDDSOC_CAP can provide. According to Table 8 of the i.MX6Q Datasheet that would be around 2A and take that as an maximum in order to be safe.