Hello,
In i.MX 6Dual/6Quad Applications Processor Reference Manual (imx6dqrm.pdf )
I see the following -
12.3.2 Core configuration
Table 12-4. Cortex-A9 Core configuration
PRELOAD_ENGINE_PRESENT - No
Does that mean that no automatic cache preload functionality is available on imx6?
Does that mean that PLD assembly instruction could not be used to optimize memory reads?
Thanks.
Hi,
Sorry for the delay,
It seems that you may use them but I suggest you to take a look at the errata first:
www.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
Regards,
Alejandro