Hi :
Our project is based on i.mx8mq-evk, which use model:MT53B768M32D4NQ-062 of lpddr4, In a recent update,we change the lpddr4 from MT53B768M32D4NQ-062 to MT53E768M32D4DT-046.
The main difference between these two is that MT53B768M32D4NQ-062 working on a freq of 1600M, while MT53E768M32D4DT-046 's freq is 2133M.
So, I simply changed the lpddr4 PLL-setting from 800M to 1066M by modifying u-boot
void ddr_init(struct dram_timing_info *dram_timing){
...
//dram_pll_init(DRAM_PLL_OUT_800M);
dram_pll_init(DRAM_PLL_OUT_1066M); // I add the 1066M register configuration code to u-boot.
...
}
From running a ddr4 testing application(mbw), It shows that the modification is worked, the ddr4 get higher read/write performance.
But when I running the memtester to do a stress testing, It always failed, I have no idle that how to solve this problem, could you please offer some precious advice?
ps:
I notice that in the early stage of u-boot, System will do a ddrphy-training, The training freq covering 800M/400M/167M.
But, I don't know how to do this training with freq of 1066M because I have no idle about training firmware configuration.
u-boot version: imx_v2018.03_4.14.98_2.0.0_ga
Thanks.
Best Regards.
downey.
