Can the cores interrupt each other in i.MX6?

[JimSung]

Can the cores interrupt each other in i.MX6?  I don't see it in the reference manual.

[max_tsai]

hi, you may refer to "uboot-imx/include/asm-arm/arch-mx6/mx6.h"

/* Cortex-A9 MPCore private memory region */

#define ARM_PERIPHBASE              0x00A00000

#define SCU_BASE_ADDR               (ARM_PERIPHBASE)

#define IC_INTERFACES_BASE_ADDR     (ARM_PERIPHBASE + 0x0100)

#define GLOBAL_TIMER_BASE_ADDR      (ARM_PERIPHBASE + 0x0200)

#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)

#define IC_DISTRIBUTOR_BASE_ADDR    (ARM_PERIPHBASE + 0x1000)

[YixingKong · Accepted solution]

JimSung, did MaxTsai andswer your question? If yes, please click Correct Answer so that we can close the DI.

Thanks,

[max_tsai]

hi Jim,

I may not get your point. ARM multiple-cores use the same interrupt controller, and it seems unable to interrupt specific CPU core by this controller.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CCHDBEBE.html

[max_tsai]

Correct my previous reply. This register can meet the requirement.

Software Generated Interrupt Register (ICDSGIR)

[23:16]

CPUTargetList

When TargetList Filter = 0b00, defines the CPU interfaces the Distributor must send the interrupt to. Each bit of CPUTargetList[7:0] refers to the corresponding CPU interface, for example CPUTargetList[0] corresponds to CPU interface 0. Setting a bit to 1 sends the interrupt to the corresponding interface.

//"arch/arm/common/gic.c"

508 #ifdef CONFIG_SMP

509 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)

510 {

511         unsigned long map = *cpus_addr(*mask);

512

513         /*

514          * Ensure that stores to Normal memory are visible to the

515          * other CPUs before issuing the IPI.

516          */

517         dsb();

518

519         /* this always happens on GIC0 */

520         writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);

521 }

522 #endif

[fatalfeel]

P91 Software Generated Interrupt Register (ICDSGIR)

http://web.uvic.ca/~etcwilde/Kernel_Development/files/docs/arm_interrupt_controller.pdf

[alexanderburaga]

Could you tell what is the address of

ICDSGIR

register in the i.mx6q memory MAP?