Brokenly swap DDR data line on imx6sl

[AccuJie]

Hi,

We are designing a customized imx6slevk board. For swapping data line of DDR3, according to the “Hardware Development Guide”, it said ‘No restrictions for complete byte lane swapping’ and ‘D0, D8, D16, D24, D32, D40, D48, and D56 are fixed’. So, can we swap DDR data line brokenly([0-7] unused, [16-23]unused) like following picture? If yes, how can we mapping high data bus to lower memory address?

Also, it noted ‘ target DDR IC register read value must be transposed according to the data line swapping.’ So, what should be done to modify ‘DDR IC register’.

Best Regards,

Jie

[igorpadykov · Accepted solution]

Hi AccuJie

I am afraid such "brokenly([0-7] unused"  from i.MX side connection

is not supported. In general for mapping one can look at

DSIZ field MMDC_MDCTL register in sect.31.12.1 MMDC Core Control Register (MMDC_MDCTL)

i.MX 6SoloLite Applications Processor Reference Manual

"target DDR IC register read value" is not applicable to ddr3.

Best regards
igor