I am wondering about the Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn) register.
It is defined here:
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 6, 05/2020
18.7.8 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn)
The problem I have is the following:
The first 7 bits are the integer part of the multiplier, and in the description of this bit array it says:
DIV_SELECT - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
I am able to write in this area value of 6, which is way below the allowed range.
Why it does allow the rate of 6 (with the fraction it is 6.144), and does the following:
To explain more directly: 6 << 27!!!
pll4_bypass_src 0 0 24000000 0 0
pll4 0 0 147456000 0 0
pll4_bypass 0 0 147456000 0 0
pll4_audio 0 0 147456000 0 0
Any logical explanation of this significant problem???
zee_z
_______