About the SSI Transmitter Timng with Internal Clock of i.MX6DL.

[takashitakahash]

Hi community.

Our customer has below questions.

The following questions about the SSI Transmitter Timng with Internal Clock of i.MX6DL.

From the timing provisions of the SSI, can not read Timing SPEC of the following, 

Describ on IMX6SDLAEC sect 4.11.19.1 SSI Transmitter Timming with Internal Clock.

Would you Please tell us about each of the specification below    Max / Typ / Min.

· TXCDuty

· TXFS_Duty

· TXD setup time

· TXD hold time

[art · Accepted solution]

1. According to the TXC clock min. period and TXC clock high/low min. period values, the TXC min./typ./max. duty cycle value can be calculated as 44.2% / 50% / 55.8 % .

2. The duty cycle parameter for the TXFS signal seems to be meaningless, since the TXFS signal waveform  depends on many programmable parameters, such as active signal width (bit wide or word wide), word length, number of words in a frame etc.

3. Since the TXD signal is generated internally to the SSI module, the TXD setup and hold time parameters seem to be meaningless for the SSI operation in Master (internal clock) mode. Instead, there is the SS17 timing parameter that specifies the maximum time between the TXC rising edge and next valid TXD data (the minimum value is 0). The data then are latched by an external device on the falling edge of TXC.

Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------