About imx8mp EVK iomuxc default value

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About imx8mp EVK iomuxc default value

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shinichiro_adac
Contributor I

Hi,

I am using i.MX8M PLUS EVK.
I am investigating the default value of iomuxc register.

For example, The value of MX8MP_IOMUXC_HDMI_DDC_SCL is as follows.

 

root@imx8mpevk:~# cat /sys/kernel/debug/pinctrl/pinctrl-maps
...
device 30330000.pinctrl
state default
type CONFIGS_PIN (3)
controlling device 30330000.pinctrl
pin MX8MP_IOMUXC_HDMI_DDC_SCL
config 000001c3

On the other hand, the register definition in the [i.MX 8M Plus Applications Processor Reference Manual]
is as follows.

SW_PAD_CTRL_PAD_HDMI_DDC_SCL.PNG


0x01c3 = 0001 1100 0011

It looks like the Reserved bit[0] is set to 1. What is the meaning of this?

Or, Is the register definition I'm referring to incorrect?

Thank you!

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1 Solution
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Yuri
NXP TechSupport
NXP TechSupport

@shinichiro_adac 
Hello,

  real configuration of the pin is as following:

root@imx8mpevk:/unit_tests# ./memtool -32 0x303304a0 1
E
Reading 0x1 count starting at address 0x303304A0

0x303304A0: 000001C2

 

  The reserved bit is not used.

Regards,
Yuri.

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3 Replies
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shinichiro_adac
Contributor I

@Yuri 

> real configuration of the pin is as following:

Thank you for your reply.
I dumped all PAD/PINMUX registers in the same way.

By the way, the configuration of the pin is defined in DTS as follows.

https://source.codeaurora.org/external/imx/linux-imx.git
branch:lf-5.10.72-2.2.0

[arch/arm64/boot/dts/freescale/imx8mp-evk.dts]

&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;

pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019
>;
};

1c3 = 0001 1100 0011

MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL bit0 is set as 1.


Why is bit0 set in DTS?
If it is not set to the reserved bit, does it mean something else?


Thanks!

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BiyongSUN
NXP Employee
NXP Employee

 

It is the information about chip default pad mux and pad ctl in datasheet you want to know?

 

Untitled.png

 

790 Views
Yuri
NXP TechSupport
NXP TechSupport

@shinichiro_adac 
Hello,

  real configuration of the pin is as following:

root@imx8mpevk:/unit_tests# ./memtool -32 0x303304a0 1
E
Reading 0x1 count starting at address 0x303304A0

0x303304A0: 000001C2

 

  The reserved bit is not used.

Regards,
Yuri.