Hello,
For the settings of Full Speed Phase Selection and Full Speed Delay Selection, is the value of QuadSPIx_SMPR [DDRSMP] updated in DDR mode?
How many QuadSPIx_SMPR [DDRSMP] do you support for each of the examples below?
Example 1
Full Speed Phase Selection: 0
Full Speed Delay Selection: 1
Example 2
Full Speed Phase Selection: 1
Full Speed Delay Selection: 0
best regards
Goto
hello,
I haven't received an answer back, so I'll change the question.
Is the correspondence of the QSPI_SMPR [DDRSMP] register for Full Speed Phase Selection and Full Speed Delay Selection (Table 6-50 in the Reference Manual) in DDR mode as follows?
Full Speed Phase Selection | 0 | 1 | 0 | 1
________________________________________________________
Full Speed Delay Selection | 0 | 0 | 1 | 1
=====================================================
QSPI_SMPR [DDRSMP] | 0 | 1 | 2 | 3
Regards,
Goto
Hello,
Please tell me the correspondence between Full Speed Phase Selection and Full Speed Delay Selection with QSPI_SMPR [DDRSMP].
As an example, please tell us about two cases.
What is QSPI_SMPR [DDRSMP] set when Full Speed Phase Selection is "1" and Full Speed Delay Selection is "0"?
What is QSPI_SMPR [DDRSMP] set when Full Speed Phase Selection is "1" and Full Speed Delay Selection"1"?
Regards,
Goto