ADV7181 on IMX6Q board

[stevetsai]

We are using ADV7181c on our board with iMX6Q and I am trying to modify adv7180.c for ADV7181. I have two questions when I modified the driver.

1.   In adv7180_hard_reset function, there are many settings for adv7180 in i.mx6 platform, but there are just a few settings in i.mx53 platform. Why do we need so many settings. By the way, there are some registers in the function that I do not see in adv7180 data sheet. For example, we can see adv7180_write_reg(0xF1, 0x19) in adv7180_hard_reset function, but there is no 0xF1 address in the data sheet.

2. Do anyone capture image from ADV7180 on iMX6Q board sucessfully? Right now I could measure the signals on LLC and data pins, but I still can not use mxc_v4l2_tvin.out to capture video. I always got the following error. How can I verify the problem?  Is it caused by adv7180.c? Thanks.

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

VIDIOC_DQBUF failed.

[qiang_li-mpu_se]

For 1, those settings are not important, in fact the iMX53 adv7180 setting can also work on iMX6.

For 2, I think the main issue is that you haven't set adv7181 correct to output BT656 interlace data.

[stevetsai]

Thanks Qiang. But adv7181 is similar to adv7180 and they have the same registers. According to the ADV7181 data sheet, these settings in ADV7180 should work with ADV7181. These settings will set adv7181 to output BT565 interface data. By the way, if I set p->u,bt656.clock_curr to 27000000 in ioctl_g_ifparm and make capture use the gated_clk mode, I will get  split image and there is no timeout error. I will upload the image later.

Hi Alberto, welcome to join the discussion.

[qiang_li-mpu_se]

    For adv7181, you can try the followed settting:

p->if_type = V4L2_IF_TYPE_BT656;

p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;

p->u.bt656.nobt_hs_inv = 0;

p->u.bt656.bt_sync_correct = 0;  // Use internal VSYNC mode, CSI_VSYNC and CSI_HSYNC pins are not needed.

p->u.bt656.clock_curr = 0;  //BT656 interlace clock mode

   adv7181 I2C register setting for CVBS input:

adv7180_write_reg(0x00,0x00);

adv7180_write_reg(0x03,0x0c);

adv7180_write_reg(0x04,0x77);

adv7180_write_reg(0x17,0x41);

adv7180_write_reg(0x1d,0x47);

adv7180_write_reg(0x31,0x02);

adv7180_write_reg(0x3a,0x17);

adv7180_write_reg(0x3b,0x81);

adv7180_write_reg(0x3d,0xa2);

adv7180_write_reg(0x3e,0x6a);

adv7180_write_reg(0x3f,0xa0);

adv7180_write_reg(0x86,0x0b);

adv7180_write_reg(0xf3,0x01);

adv7180_write_reg(0xf9,0x03);

adv7180_write_reg(0x0e,0x80);

adv7180_write_reg(0x52,0x46);

adv7180_write_reg(0x54,0x00);

adv7180_write_reg(0x7f,0xff);

adv7180_write_reg(0x81,0x30);

adv7180_write_reg(0x90,0xc9);

adv7180_write_reg(0x91,0x40);

adv7180_write_reg(0x92,0x3c);

adv7180_write_reg(0x93,0xca);

adv7180_write_reg(0x94,0xd5);

adv7180_write_reg(0xb1,0xff);

adv7180_write_reg(0xb6,0x08);

adv7180_write_reg(0xc0,0x9a);

adv7180_write_reg(0xcf,0x50);

adv7180_write_reg(0xd0,0x4e);

adv7180_write_reg(0xd1,0xb9);

adv7180_write_reg(0xd6,0xdd);

adv7180_write_reg(0xd7,0xe2);

adv7180_write_reg(0xe5,0x51);

adv7180_write_reg(0xf6,0x3b);

adv7180_write_reg(0x0e,0x00);

[stevetsai]

Hi Qiang,

     I used the above settings in video decoder driver, but I still got the following error.

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

If I just change to following code, I will got the following video and ipu_csi will enable VDI in ipu_enable_channel function.

     p->u.bt656.clock_curr = 27000000;

Here are the values in register 0x10 to 0x13.

0x10=0d

0x11=19

0x12=40

0x13=69

[qiang_li-mpu_se · Accepted solution]

    When p->u.bt656.clock_curr = 0, it is BT656 interlaced mode, in this mode, the CSI will check the data bus for EAV and SAV, it will only capture the video data after found the correct EAV and SAV.

    But for p->u.bt656.clock_curr != 0, it is gated clock mode, in this mode, the CSI will capture data all the time when there is pixel clock, VSYNC and HSYNC, it will not check the data bus.

    So for your case, I think you need capture the data bus by some device to check if there is EAV and SAV code.

[sharathm]

Hi Qiang Li,

Here i am also trying to interface adv7180 with imx6q_sabrelite board, but as per your suggestion i tried changing  p->u.bt656.clock_curr to 0 but still the problem persists. Can you please help me with this.

[rajanpatel]

Hey sharathm‌ ,

   i am also trying to interface ADV7180 with IMX6q(csi0). i am using non-gated clock mode and p->u.bt656.clock_curr = 0.

i am getting same error 'ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0'. i am attaching my dynamic debug messages. i am using buildroot2016

please help.

Regards,

rajanpatel‌

[qiang_li-mpu_se]

You can check this document for TVin use case.

https://community.nxp.com/docs/DOC-332679

[charlesung]

The link to the document seems to be broken. Can you provide us a way to access the document please? To be exact, it said I am not authorized to access the page.

[stevetsai]

Hi Qiang,

     I used two different video devices. One is SONY video CAM recorder and another is CCD video CAM. Both of them support NTSC video format, but I will check them again. By the way, if I use gated clock mode, I should get the correct video when the pixel clock, VSYNC and HSYNC are correct. Does it means that these signals on my board have problem?  

[qiang_li-mpu_se]

From your picture, I think you can't use gated clock mode, there is blanking data for each line that had been captured.

[stevetsai]

Hi Qiang,

If I set the bt_sync_correct to 1, it means that CSI uses the external vsync, right? Does CSI still need the embedded synchronous data for hsync? 

p->u.bt656.bt_sync_correct = 1;

[qiang_li-mpu_se]

For bt_sync_correct = 1, the embedded synchronous data is also needed. The difference for bt_sync_correct = 1 or 0 is that CSI_VSYNC/HSYNC pins are needed or not.

[stevetsai]

Hi Qiang,

CSI can use CSI_VSYNC and CSI_HSYNC or jsut leave them alone. What's situation I have to use VSYNC/HSYNC? What's situation I do not use VSYNC/HSYNC? These two signals seem useless. Thanks.

[qiang_li-mpu_se]

    For BT656 clock mode, VSYNC and HSYNC are not necessary, but for gated and non-gated clock mode they are must.

    By the way, the CSI also has the capability to reference the VSYNC and HSYNC signal for BT656 clock mode. And if you can make sure your sensor will always work in BT656 clock mode, then you can reserve these two pins as other function. Using or not using these two pins, it depends on your use case.

[stevetsai]

BT.656 only support 8 or 10 bits, so I should use V4L2_IF_TYPE_BT1120_MODE_BT_16BIT. I know ADV7181c supports 16bits data bus, but I did not find BT.1120 setting in ADV7181 data sheet. How do you use V4L2_IF_TYPE_BT1120_MODE_BT_16BIT with ADV7180?

[qiang_li-mpu_se]

For iMX6 BSP, the BT1120 16bits mode was not ready yet, we don't have the real hardware to enable it. Maybe you need reference to the iMX53 patch to support it.

[stevetsai]

Yes, we are doing the job now. Do you use BT1120 16bits mode on iMX53 with ADV7180? I did not see ADV7180 use this mode. Thanks.

[donfreiling]

I am also trying to get ADV7181 working with MX6. Would it be possible to post the changes that you made to adv7180.c in order get it working. I am also using a BT1120 16bit mode.

Regards

[qiang_li-mpu_se]

I had enabled BT1120 16bits mode on iMX53 with ADV7842 chip. In fact, the TV decoder chip is not important, you only need make sure it outputs BT1120 16bits data, the CSI and IPU side codes are same for all decoder chip.