25MHz reference clock output from ENET0 block of iMX8XL/DXL

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

25MHz reference clock output from ENET0 block of iMX8XL/DXL

838 Views
chirag_patel1
Contributor I

Hello, we want to get rid of 25MHz PHY crystal and wondering if

-- iMX8XL/DXL can output this reference clock to inject into XI pin of the PHY.

-- What pin would this clock output be available on?

--  What Alternate function enables this function?

--  How to set this output clk freq to 25MHz? (PLL multiplier/divider values, register address)

Thanks in advance!

0 Kudos
Reply
1 Reply

771 Views
jimmychan
NXP TechSupport
NXP TechSupport

The pin is ENET0_REFCLK_125M_25M.

Please refer to NXP released BSP, there is SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M. We do not use this by default, but it is included in the code.

Please set IOMUX for SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M.

Then use the following SCFW API function call to enable the 25MHz clock output on that pin:

 

sc_misc_set_control(ipc, SC_R_ENET_0, SC_C_SEL_125, 0);  // 0=25Mhz, 1=125MHz

sc_misc_set_control(ipc, SC_R_ENET_0, SC_C_DISABLE_125, 0); 

0 Kudos
Reply